Verilog--continued

Verilog--continued

Next State Current State Next-State Logic Memory Inputs Finite State Machine (FSM) • All state machines have the general feedback structure consisting of: • Combinational logic implements the next state logic • Next state (ns) of the machine is formed from the current state (cs) and the current inputs • State register holds the value of current state

Next-State Logic State Register Output Logic Types of State Machines Moore State Machine—example? cs ns Inputs Outputs • Next state depends on the current state and the inputs but the output depends only on the present state • next_state(t) = h(current_state(t), input(t)) • output = g(current_state(t))

Types of State Machines (cont.) Mealy State Machine—example? Output Logic Outputs cs ns Next-State Logic State Register Inputs • Next state and the outputs depend on the current state and the inputs • next_state(t) = h(current_state(t), input(t)) • output(t) = g(current_state(t), input(t))

Typical Structure of a FSM module mod_name ( … ); input … ; output … ; parametersize = … ; reg[size-1: 0] current_state; wire[size-1: 0] next_state; // State definitions `definestate_0 2'b00 `definestate_1 2b01 always @ (current_state or the_inputs)begin // Decode for next_state with case or if statement // Use blocked assignments for all register transfers to ensure // no race conditions with synchronous assignments end always @(negedgereset or posedgeclk) begin if (reset == 1'b0) current_state <= state_0; else current_state <= next_state; end //Output assignments endmodule Next State Logic State Register

Another FSM example: sequence detector: detect two successive 0s or 1s in the input stream module detect(…) input …; output …; reg …; reg[…] state; parameter always @(state) begin case (state) … always @(…) begin … end endmodule reset reset_state out_bit = 0 0 1 1 read_1_zero read_1_one out_bit = 0 out_bit = 0 0 0 0 1 1 read_2_zero read_2_one 0 1 out_bit = 1 out_bit = 1

read_1_zero: if(in_bit == 0) next_state = read_2_zero; else if(in_bit == 1) next_state = read_1_one; elsenext_state = reset_state; read_2_zero: if (in_bit == 0) next_state = read_2_zero; else if(in_bit == 1) next_state = read_1_one; else next_state = reset_state; read_1_one: if (in_bit == 0) next_state = read_1_zero; else if(in_bit == 1) next_state = read_2_one; elsenext_state = reset_state; read_2_one: if(in_bit == 0) next_state = read_1_zero; else if(in_bit == 1) next_state = read_2_one; elsenext_state = reset_state; default: next_state = reset_state; endcase assignout_bit = ((state_reg == read_2_zero) || (state_reg == read_2_one)) ? 1 : 0; endmodule module seq_detect (clock, reset, in_bit, out_bit); inputclock, reset, in_bit; outputout_bit; reg[2:0] state_reg, next_state; // State declaration parameterreset_state = 3'b000; parameterread_1_zero = 3'b001; parameterread_1_one = 3'b010; parameterread_2_zero = 3'b011; parameterread_2_one = 3'b100; // state register always @(posedgeclock or posedgereset) if(reset == 1) state_reg <= reset_state; else state_reg <= next_state; // next-state logic always @ (state_reg or in_bit) case (state_reg) reset_state: if (in_bit == 0) next_state = read_1_zero; else if (in_bit == 1) next_state = read_1_one; else next_state = reset_state;

Testbenches: A type of verilog file; used to drive simulation, report results

Simulation statements: Display tasks $display : Displays the entire list at the time when statement is encountered $monitor : Whenever there is a change in any argument, displays the entire list at end of time step Simulation Control Task $finish : makes the simulator to exit $stop : suspends the simulation Time $time: gives the simulation

Example: `timescale 1ns/100ps module Top; reg PA, PB; wire PSum, PCarry; HalfAdder G1(PA, PB, PSum, PCarry); initial begin: LABEL reg [2:0] i; for (i=0; i<4; i=i+1) begin {PA, PB} = i; #5 $display (“PA=%b PB=%b PSum=%b PCarry=%b”, PA, PB, PSum, PCarry); end // for end // initial endmodule

Test Bench - Generating Stimulus Example: A sequence of values initialbegin Clock = 0; #50 Clock = 1; #30 Clock = 0; #20 Clock = 1; end

Test Bench - Generating Clock • Repetitive Signals (clock) Clock • A Simple Solution: wire Clock; assign #10 Clock = ~ Clock • Caution: • Initial value of Clock (wire data type) = z • ~z = x and ~x = x

Test Bench - Generating Clock (cont.) • Initialize the Clock signal initialbegin Clock = 0; end • Caution: Clock is of data type wire, cannot be used in an initial statement • Solution: reg Clock; … initial begin Clock = 0; end … always begin #10 Clock = ~ Clock; end forever loop can also be used to generate clock

Types of Port Connections parent_mod Connection by Position

Type of Port Connections (cont.) parent_mod Connection by Name

Empty Port Connections • If an input port of an instantiated module is empty, the port is set to a value of z (high impedance). module child_mod(In1, In2, Out1, Out2) module parent_mod(…….) input In1; input In2; child_mod mod(A, ,Y1, Y2); output Out1; //Empty Input output Out2; endmodule //behavior relating In1 and In2 to Out1 endmodule • If an output port of an instantiated module is left empty, the port is considered to be unused. module parent_mod(…….) child_mod mod(A, B, Y1, ); //Empty Output endmodule

Physical layout:Synthesis of Combinational Logic – Gate Netlist Synthesis tools further optimize a gate netlist specified in terms of Verilog primitives Example: module or_nand_1 (enable, x1, x2, x3, x4, y); inputenable, x1, x2, x3, x4; outputy; wirew1, w2, w3; or(w1, x1, x2); or(w2, x3, x4); or(w3, x3, x4); // redundant nand(y, w1, w2, w3, enable); endmodule Q: what technology is this? What Might the post-synthesis Altera circuit look like?

Synthesis of Combinational Logic – Gate Netlist (cont.) General Steps: Logic gates are translated to Boolean equations. The Boolean equations are optimized. Optimized Boolean equations are covered by library gates. Complex behavior that is modeled by gates is not mapped to complex library cells (e.g. adder, multiplier) The user interface allows gate-level models to be preserved in synthesis.

Synthesis of Combinational Logic – Continuous Assignments Example: module or_nand_2 (enable, x1, x2, x3, x4, y); inputenable, x1, x2, x3, x4; outputy; assigny = !(enable & (x1 | x2) & (x3 | x4)); endmodule

Synthesis of Combinational Logic – Behavioral Style Example: module or_nand_3 (enable, x1, x2, x3, x4, y); inputenable, x1, x2, x3, x4; outputy; regy; always@(enable orx1 orx2 orx3 orx4) if(enable) y = !((x1 | x2) & (x3 | x4)); else y = 1; // operand is a constant. endmodule Note:Inputs to the behavior must be included in the event control expression, otherwise a latch will be inferred.

Synthesis of Combinational Logic – Functions Example: module or_nand_4 (enable, x1, x2, x3, x4, y); inputenable, x1, x2, x3, x4; outputy; assigny = or_nand(enable, x1, x2, x3, x4); functionor_nand; inputenable, x1, x2, x3, x4; begin or_nand = ~(enable & (x1 | x2) & (x3 | x4)); end endfunction endmodule

Constructs to Avoid for Combinational Synthesis • Edge-dependent event control • Multiple event controls within the same behavior • Named events • Feedback loops • Procedural-continuous assignment containing event or delay control • wait statements • Procedural loops with timing • Data dependent loops

Unwanted Latches • Unintentional latches generally result from incomplete case statement or conditional branch • Example: case statement always @ (sel_a orsel_b ordata_a ordata_b) case({sel_a, sel_b}) 2'b10: y_out = data_a; 2'b01: y_out = data_b; endcase The latch is enabled by the "event or" of the cases under which assignment is explicitly made. e.g. ({sel_a, sel_b} == 2'b10) or ({sel_a, sel_b} == 2'b01)

Unwanted Latches (cont.) • Example: if .. else statement always @ (sel_a orsel_b ordata_a ordata_b) if({sel_a, sel_b} == 2’b10) y_out = data_a; else if ({sel_a, sel_b} == 2’b01) y_out = data_b;

Priority Logic • When the branching of a conditional (if) is not mutually exclusive, or when the branches of a case statement are not mutually exclusive, the synthesis tool will create a priority structure. • Example: module mux_4pri (y, a, b, c, d, sel_a, sel_b, sel_c); inputa, b, c, d, sel_a, sel_b, sel_c; outputy; regy; always @(sel_a orsel_b orsel_c ora orb orc ord) begin if(sel_a == 1) y = a; else if(sel_b == 0) y = b; else if(sel_c == 1) y = c; else y = d; end endmodule

VERILOG: Synthesis - Sequential Logic • General Rule: A variable will be synthesized as a flip-flop when its value is assigned synchronously with an edge of a signal. • Example: module D_reg4a (Data_in, clock, reset, Data_out); input[3:0] Data_in; inputclock, reset; output[3:0] Data_out; reg[3:0] Data_out; always @(posedge reset or posedge clock) if(reset == 1'b1) Data_out <= 4'b0; elseData_out <= Data_in; endmodule

Registered Combinational Logic • Combinational logic that is included in a synchronous behavior will be synthesized with registered output. • Example: module mux_reg (a, b, c, d, y, select, clock); input[7:0] a, b, c, d; output[7:0] y; input[1:0] select; reg[7:0] y; always @(posedge clock) case(select) 0: y <= a; // non-blocking 1: y <= b; // same result with = 2: y <= c; 3: y <= d; defaulty <= 8'bx; endcase endmodule

Verilog--continued

Verilog--continued

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