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Verilog

Verilog. Section 3.10 Section 4.5. Keywords. Keywords are predefined lowercase identifiers that define the language constructs Key example of keywords: module, endmodule , input, output, and wire. assign.

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Verilog

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  1. Verilog Section 3.10 Section 4.5

  2. Keywords • Keywords are predefined lowercase identifiers that define the language constructs • Key example of keywords: module, endmodule, input, output, and wire.

  3. assign • The assignment is said to be sensitive to the variables in the RHS expression because anytime a variable in the RHS changes during the simulation, the RHS expression is reevaluated and the result is used to update the LHS.

  4. Semicolon • Each statement must end with a semicolon (;)

  5. Bitwise Logic Operation • Bitwise means 1 bit at a time

  6. wire You can think of a wire as a wire in a circuit where actual voltages Could be measured.

  7. Wire example Use & for AND operation Use tilda (~) for the INVERT operation Use | for the OR operation

  8. Waveform

  9. Using Verilog Primitives • Verilog also has keywords such as andor and not. The output of a primitive must be listed first.

  10. Gate Delays • In Verilog, the propagation delay of a gate is specified in terms of time units and is specified by the symbol #. • `timescale 1ns/100ps • The first number specifies the unit of measurement for time delays. • The second number specifies the precisions for which the delays are rounded off.

  11. Gate Delay E is not defined until after 1 ns.

  12. Gate Delay E is not defined until 1 ns. W is not defined until 2 ns. This means that D is not defined until 3 ns.

  13. Binary Addition Example

  14. Derivation of ∑ (ES112 Slides) • Question: What primitive best implements ∑? • Inputs: A, B • Outputs: ∑=

  15. Derivation of Carry Out(ES112 Slides) • Question: What primitive best implements Co? • Inputs: A, B • Outputs: Co =A∙B

  16. Implementation of a Half-Adder

  17. Limitation of a Half Adder A half-adder does not account for carry-in.

  18. Truth Table for a Full Adder carry-in

  19. Karnaugh Map For the Sum Bit(ES112 Review) = = =

  20. Karnaugh Map For the Carry-Out Bit(ES112 Review)

  21. Implementation of a Full Adder (carry-in)

  22. Schematic of a Full Adder Half-adder Half-adder(not including the bubble)

  23. Build a Verilog Representation of a Full Adder Circuit • Build a half adder circuit • Build a test bench for the adder circuit • Assemble a full adder circuit • Build a test bench circuit to test the full –adder • Write the code to implement the adder circuit on FPGA

  24. Build a Half-Adder Circuit (Figure 4.5)

  25. Build a Test Bench in Verilog Ideas: (page 112 of the textbook) reg Initial statement Assign value to a single bit $finish 1’b0=one binary digit with a value of 0 1’b1=one binary digit with a value of 1

  26. Initial, $finish • inital: keyword used with a set of statements that begin executing when simulation is initialized. • $finish: specifies the termination of simulation.

  27. Block statement A block statement consists of several statements that are executed in sequence from top to bottom.

  28. Build a Full-Adder Circuit M1 M2 w1 w2 w3

  29. Full-Adder Top Level Circuit

  30. Build a FPGA Top Level Circuit (y) (c) (x) (z) (s) See gates2.pdf (available from the course website) for reference

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