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Digital Design Lectures 11 & 12

Digital Design Lectures 11 & 12. Shift Registers and Counters. Register with Parallel Load. Register: Group of Flip-Flops Ex: D Flip-Flops Holds a Word (Nibble) of Data Loads in Parallel on Clock Transition Asynchronous Clear (Reset). Register with Load Control. Load Control = 1

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Digital Design Lectures 11 & 12

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  1. Digital DesignLectures 11 & 12 Shift Registers and Counters

  2. Register with Parallel Load • Register: Group of Flip-Flops • Ex: D Flip-Flops • Holds a Word (Nibble) of Data • Loads in Parallel on ClockTransition • Asynchronous Clear (Reset)

  3. Register with Load Control • Load Control = 1 • New data loadedon next positiveclock edge • Load Control = 0 • Old data reloadedon next positiveclock edge

  4. Shift Registers • Cascade chain of Flip-Flops • Bits travel on Clock edges (Bucket Brigade) • Serial in – Serial out, can also have parallel load / read

  5. Serial Transfer Time T0 T1 T2 T3 T4 Reg A 1011 1101 1110 0111 1011 Reg B 0011 1001 1100 0110 1011

  6. Serial Addition (D Flip-Flop) • Slower than parallel • Low cost • Share fasthardware onslow data • Good for multiplexed data

  7. Designing a JK Serial Adder • JQ = xy, KQ = xy = (x+y), S = xyQ PresentStateQ 00001111 Inputsx y 0 00 11 01 10 00 11 01 1 NextStateQ 00010111 OutputS 01101001 Flip_FlopInputs JQ KQ 0 x0 x0 x1 xx 1x 0x 0x 0 Table 6-2

  8. New Serial Adder

  9. Universal Shift Register • Clear • Clock • Shift • Right • Left • Load • Read • Control S10011

  10. A3 000000001 A2 000011110 A1 001100110 A0 010101010 Binary Ripple Counter • Asynchronouscounter • Changes “ripple”through the stages Table 6-4

  11. Decimal (BCD) Counter

  12. Synchronous Binary Counter • All transitions occur onclock pulse edges inparallel • Faster results than ripplecounters

  13. Up-Down Synchronous Counter

  14. Present StateQ8 Q4 Q2 Q1 0 0 0 00 0 0 10 0 1 0 0 0 1 10 1 0 00 1 1 00 1 0 10 1 1 11 0 0 01 0. 0 1 Next StateQ8 Q4 Q2 Q1 0 0 0 10 0 1 0 0 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0. 0 10 0 0 0 Outputy 0000000001 Next State TQ8 TQ4 TQ2 TQ1 0 0 0 10 0 1 1 0 0 0 10 1 1 10 0 0 10 0 1 10 0 0 11 1. 1 10 0 0 11 0 0 1 Designing a SynchronousBCD Counter TQ1 = 1, TQ2 = Q8Q1 , TQ4 = Q2Q1 , TQ8 = Q8Q1 + Q4Q2Q1 , y = Q8Q1

  15. Clear 0111 Clk x Load x100 Count xx10 Function ClearLoadCountNo Change 4-bit Synchronous Counterwith Parallel Load Table 6-6

  16. More BCD Counterswith Parallel Load

  17. Counters with Unused States • If in unused state • Ensure automaticreturn to a validstate • “Self-correcting”

  18. Generating Timing Pulses • Shift Register • Walk a 1 • Counter anddecoder

  19. Johnson Counter • Shift register • 2*k States • Walk 1s • Then walk 0s • Only needssimple outputlogic for timingpulses(Mealy model)

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