1 / 28

FPGA Development Boards and Schematic Entry Process Guide

Learn about Altera FPGA development boards, schematic design process, connections, project creation, pin assignment, and simulation techniques.

wpreece
Download Presentation

FPGA Development Boards and Schematic Entry Process Guide

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Figure 1.1 The Altera UP 3 FPGA Development board

  2. Figure 1.2 The Altera UP 2 FPGA development board.

  3. Figure 1.3 Design process for schematic or HDL entry.

  4. Figure 1.4 Connections between the pushbuttons, the LEDs, and the Altera FPGA.

  5. Figure 1.5a and 1.5b. Equivalent circuits for ORing active low inputs and outputs. (a) (b)

  6. Figure 1.6 Creating a new Quartus II Project.

  7. Figure 1.7 Setting the FPGA Device Type.

  8. Figure 1.8 Creating the top-level project schematic design file.

  9. Figure 1.9 Selecting a new symbol with the Symbol Tool.

  10. Figure 1.10 Active low OR-gate schematic example with I/O pins connected.

  11. Table 1.1 Hardwired connections on the FPGA chips for the design.

  12. Figure 1.11 Assigning Pins with the Assignment Editor.

  13. Figure 1.12 Active low OR-gate timing simulation with time delays.

  14. Figure 1.13 ALTERA UP 3 board showing Pushbutton and LED locations used in design

  15. Figure 1.14 ALTERA UP 2 board with jumper settings and PB1, PB2, and LED locations

  16. Table 1.2 Jumper settings for downloading to the UP2 MAX and FLEX devices.

  17. Figure 1.15 UP 2’s FLEX FPGA pin connection to seven-segment display decimal point.

  18. Figure 1.16 VHDL Entity declaration text.

  19. Figure 1.17 VHDL OR-gate model (with syntax error).

  20. Figure 1.18 VHDL compilation with a syntax error.

  21. Figure 1.19 Verilog module declaration text.

  22. Figure 1.20 Verilog active low OR-gate model (with syntax error).

  23. Figure 1.21 Verilog compilation with a syntax error.

  24. Figure 1.22 Timing analyzer showing input to output timing delays.

  25. Figure 1.23 Floorplan view showing internal FPGA placement of OR-gate in LE and I/O pins

  26. Figure 1.24 ORgate design symbol.

  27. Figure 1.14 The Altera DE2 FPGA Development board

  28. Figure 1.15 The Altera DE2 FPGA Development board

More Related