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ASU Summer Robotics Camp VPL-Based Simulation

Explore the design process with simulation, including logic design of an ALU, VPL simulation of gates, testing, and robotics simulation.

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ASU Summer Robotics Camp VPL-Based Simulation

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  1. ASU Summer Robotics Camp VPL-Based Simulation Dr. Yinong Chen

  2. Table of Contents Design Process with Simulation 1 Logic Design of an ALU 2 VPL Simulation of Gates 3 Testing 4 Robotics Simulation 5

  3. 1 Define Problem 2 Generate Solutions 3 Decide the Course of Action 4 Implement Solution Simulation 5 Evaluate Solution Design Process with Simulation:For Visualizing the Design and for Pre-Evaluation of the Implementation

  4. What is Simulation? • The process of imitating a real phenomenon with a set of mathematical formulas. • Simulation is often based on modeling: Creating mathematical models to imitating real thing. • Advanced computers and programs are the major driving force in creating useful simulations. They can simulate weather conditions, chemical reactions, atomic reactions, even biological processes. • In theory, any phenomena that can be reduced to mathematical data and equations can be simulated on a computer. • In practice, however, simulation is extremely difficult because most natural phenomena are subject to an almost infinite number of influences. • One of the challenges to developing useful simulations is to determine which are the most important factors

  5. Logic Design:Analogue versus Digital

  6. Elements of (Propositional) Logic • Proposition: A statement that can either be true or false: • One plus two is three • There is a Nobel prize winner from Arizona State University • The sky is blue • How old are you? • You must ride a bike to school! • Logic connectives • AND (), OR (), NOT (), IMPLIES () • light is on  tank is full • (Light is off)  (bulb is not broken)  tank is empty • Truth and falsity values – Truth Table

  7. a b ab • 0 0 0 • 0 1 0 • 0 0 • 1 1 1 Truth Table as a Specification NOT propositional variable statement a ¬ a false true true false AND a b a  b false false false false true false true false false true true true • a a • 0 1 • 0

  8. a b ab • 0 0 0 • 0 1 1 • 0 1 • 1 1 1 Truth Table (Contd.) OR a b a  b false false false false true true true false true true true true

  9. a a • 0 1 • 0 • a b ab • 0 0 0 • 0 1 0 • 0 0 • 1 1 1 a b • a b ab • 0 0 0 • 0 1 1 • 0 1 • 1 1 1 a b a c c c NOT gate AND gate c = ab OR gate c = a  b c = a a b a b c c NAND gate c = (ab) NOR gate c = (a  b) Building Blocks of a Computer Basic Building Blocks Truth Tables • a b (ab) (ab) ab  ab • 0 0 1 1 0 • 0 1 1 0 1 • 0 1 0 1 • 1 1 0 0 0 a b c XOR gate c = ab  ab

  10. Design my Own Computer? Yes, I can!

  11. ALU Five Modules of a Computer CPU Peripheral Memory Control logic input output Adder Bus

  12. output 8 bits = 1 Byte Can store a “character” Or a short integer 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit input Memory Design: bit and Byte output 0 1 One bit can store a “1” or a “0” input One-bit memory design

  13. 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 2 1 0 31 30 29 The Entire Memory, with 32-bit address space and byte-addressable Hex address 00000000h 00000004h 00000008h 0000000Ch 00000010h 00000014h 00000018h 0000001Ch 00000020h 00000024h 00000028h 0000002Ch 00000030h FFFFFFF0h FFFFFFF4h FFFFFFF8h FFFFFFFCh . . . . . . . . . . . . . . .

  14. a a + + sum sum b b carryOut carryOut Designing the Adder 0 a b carryIn 1 0 0 1 0 1 1 + 1 0 1 0 1 1 0 0 1 0 11 0 1 1 1 0 1 1 0 a b carryIn 3 4 5 4 6 1 8 0 7 4 1 0 1 1 0 5 2 6 2 0 . . .

  15. Simulating a One-Bit Adder Use a Computer Program in VPL to imitate the Design Design Testing

  16. a b CarryIn CarryOut Sum sum carryIn a b 0 0 0 0 0 carryOut 0 0 1 0 1 input output 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 ALU Design: one-bit adder

  17. Simulation in VPL: NOT Gate a c

  18. Simulation in VPL: OR Gate a b c

  19. Simulation in VPL: AND Gate first second output

  20. Simulation in VPL: XOR Gate a b c

  21. sum carryIn a b carryOut One-Bit Adder Define Before Using: Define the input whenever you see a warning sign

  22. Testing the One-Bit Adder

  23. One-Bit ALU

  24. Define Before Using: Define the input whenever you see a warning sign

  25. Testing the One-Bit ALU op0 op1 op2 carryIn first second One_Bit_ALU

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