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Comprehensive Overview of Memory CTL Pin Level Functions

This document outlines the CTL construct for defining all memory pins affecting memory tests, ensuring seamless integration with test protocols. It details various pin attributes such as Name, Range, Direction (Input, Output, InOut), Polarity (Active High/Low), and numerous functional operations including Read/Write enables, clock functions, and error correction techniques. Additionally, it includes specifications for different pin types relevant to ECC, power control, and memory repair functionalities. This thorough review aims to standardize memory pin definitions and support test integration.

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Comprehensive Overview of Memory CTL Pin Level Functions

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  1. Memory CTL Pin Level Functions

  2. Pin Level Functions • Members • Sirinvas, Karen, Nicco • Scope: • Define CTL construct to describe all memory pins that may affect memory test to enable seamless integration of Test • Pin Information • Pin Name • Pin Range [L..R] • Direction (Input, Output, InOut) • Logical Port relationship • Polarity (Active High/Low) • Pin Function Data, Address, BistClock, ReadEnable, WriteEnable, ReadWriteEnable, MasterClock, BistEnable, SlaveClock, ScanClock, GroupWriteEnable, GroupReadWriteEnable, (None), Open, OutputEnable, ScanTest, ByPassEnable, MemSelect, ShiftEnable, Active, CAS, RAS, Refresh, ECCDisable, PipelineEnable, [User defined], CAMComparandInput, CAMComparandMask, CAMCompareEnable, CAMMatchOutput, CAMMatch, CAMMultiHit, CAMMatchAddress; ECCEnable, ECCTestInput, ECCDataOutput, ECCOuputEnable, <Repair Related Functions>, <Timing Margin Related Functions>, <ECC Correction>, <ECC Error>, <Power Down Functions>, <CAM Reset>, <Scan Clock Enable>, <Sync bypass Clock>, <MRAMs pin functions>, <Flash Memory Pin Functions>, <External memory pins>, <NVM pins>, • Mile Stone: Draft Document by Feb 2007 (first draft completed in March 2007) • Converted to IEEE standard format: May 2007

  3. Pin Level Functions • Reusing existing Datatypes (21) • MemoryData, MemoryAddress, CoreSelect, OutEnable, MasterClock, MemoryWrite, MemoryRead, ScanMasterClock, ScanSlaveClock, ScanEnable, ScanDataIn, ScanDataOut, In, Out, InOut, Constant, TestData, TestControl, UnusedDuringTest, Row, Column. • Can use more than one type to define a pin function

  4. Pin Level Functions • New types introduced (23) • ScanBypassClock, ColumnAddressSelect, RowAddressSelect, RefreshClock, RefreshClockSelect, ECCEnable, ECCData, ColumnRepairEnable, RowRepairEnable, ColumnRepairData, RowRepairData, TimingMarginSelect, AsyncWriteThrough, GroupWriteEnable, ScanTest, CAMCompareandInput, CAMCompareandMask, CAMCompareEnable, CAMMatchOutput, CAMMatch, CAMMultiHit, CAMMatchAddress, CAMReset. • New Keyword in relation block • WriteEnableMap

  5. Pin Level Functions • New types to be defined • Open, Active, PipelineEnable, ECCOutputEnable, <Power pins>, <MRAM pins>, <Flash memory pins>, <External memory pins>, <NV memory pins>

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