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EECE 320 Digital Systems Design Lecture 15: Combinational Logic Design Practices

EECE 320 Digital Systems Design Lecture 15: Combinational Logic Design Practices. Ali Chehab. 74x148 Priority Encoder. Inputs and Outputs are active low GS asserted if EI asserted and 1 or more Inputs are asserted

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EECE 320 Digital Systems Design Lecture 15: Combinational Logic Design Practices

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  1. EECE 320Digital Systems DesignLecture 15: Combinational Logic Design Practices Ali Chehab

  2. 74x148 Priority Encoder • Inputs and Outputs are active low • GS asserted if EI asserted and 1 or more Inputs are asserted • EO asserted if EI is asserted but no input is asserted, could be connected to another EI (lower priority)

  3. 32-to-5 Priority Encoder – 4 (74x148) GS signals are used as a 4-to-2 encoder to set the values of RA4 and RA3 RA3 = GS1 + GS3 RA4 = GS2 + GS3 RGS is asserted if any GS is asserted The outputs A2-A0 of at most one 74x148 will be enabled at any time. They can be ORed to produce RA2-RA0 MSB 11 11000 11111 MSB 10 10000 10111 MSB 01 01000 01111 MSB 00 00000 00111

  4. VHDL 8-to-3 Priority Encoder library IEEE; use IEEE.std_logic_1164.all; entity encoder8to3 is port ( I: in STD_LOGIC_VECTOR (7 downto 0); A: out STD_LOGIC_VECTOR (2 downto 0) ); end encoder8to3; architecture encoder8to3 of encoder8to3 is

  5. VHDL 8-to-3 Priority Encoder function CONV_STD_LOGIC_VECTOR(arg: integer; size: integer) return std_logic_vector is variable result : std_logic_vector(size-1 downto 0); variable temp : integer; begin temp := arg; for i in 0 to size-1 loop if (temp mod 2) = 1 then result(i) := '1'; else result(i) := '0'; end if; temp := temp/2; end loop; return result; end;

  6. VHDL 8-to-3 Priority Encoder begin process (I) variable j: integer range 7 downto 0; begin for j in 7 downto 0 loop if I(j) = '1' then A <= CONV_STD_LOGIC_VECTOR(j, 3); exit; end if; end loop; end process; end encoder8to3;

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