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Low Power Solutions: A System Design Perspective. Nik Sumikawa. Low Power: Why?. 1. Standard Embedded Solutions. 2. 3. 3. Innovative Solutions. 4. 4. Solutions for Mobile Platforms. Contents. Low Power: Why?. Power vs. Performance Technology Scaling VLSI Embedded Technology Trend

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contents

Low Power: Why?

1

Standard Embedded Solutions

2

3

3

Innovative Solutions

4

4

Solutions for Mobile Platforms

Contents
low power why
Low Power: Why?
  • Power vs. Performance
  • Technology Scaling
    • VLSI
    • Embedded
  • Technology Trend
    • Green Stimulus
    • Scaling Size

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what you should think about
What You Should Think About
  • Low power design strategies
    • Components: Microcontrollers, peripherals, ect.
    • Low power design with hardware
    • Low power design with software
    • Low power design in mobile device

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low power embedded systems
Low Power Embedded Systems
  • TELOS:
    • Low power wireless embedded system
    • Low duty cycle principle
    • Minimizes dynamic power consumption

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low duty cycle principle

Process

Wake

Up

Sleep Mode

Sleep

Prep

Deep

Sleep

Low Duty Cycle Principle

Timer or Interrupt event

low duty cycle
Low Duty Cycle
  • Low processing to sleep ratio
    • Extended sleep period
  • Responsively:
    • fast wake-up and sleep times
  • Minimize Interrupts:
    • Context switching overhead

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low duty cycle dma
Low Duty Cycle: DMA
  • Direct Memory Access (DMA):
    • Controls bus and transfers data with minimal processor overhead
  • Significance
    • Transfer data while sleeping
    • Minimize processor overhead

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low duty cycle1
Low Duty Cycle
  • Fails with significant processing
  • Alternatives:
    • Dynamic Voltage and Frequency Scaling (DVFS)
    • Dynamic Power Management (DPM)
  • Image: http://www.domainmagnate.com/wp-content/uploads/2009/03/failure-success.jpg
dynamic power

Design Variables

Energy Source

Capacitance

Dynamic

Power

Frequency

Battery

Voltage

P = CVdd2f

Dynamic Power
reducing dynamic power
Reducing Dynamic Power
  • Dynamic Voltage and Frequency Scaling
  • Scale voltage when sleeping/Idle
    • Voltage term quad. proportional to power
  • Reduce frequency
  • Minimize line capacitance
    • Long traces have large capacitance

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dynamic power management
Dynamic Power Management
  • Generalize power management
  • Multiple policies
    • Single-policy
    • Multiple-policy
    • Task-scaling

Rajami and Brock [2]

single policy strategy
Single-policy Strategy
  • Idle Scaling (IS)
    • Operate at full speed when processing workload
    • Reduce the frequency and voltage when idle
  • Goal:
    • Reduce the CPU and bus frequencies
    • Meet continuous DMA requirements
    • Provide acceptable latency when resuming from idle

Rajami and Brock [2]

multi policy strategies
Multi-policy Strategies
  • Load scaling (LS):
    • Balance system operating point with current or predicted processing demands
    • Run system with minimal idle time
  • Other:
    • Manage systems state based on status of the systems energy source

Rajami and Brock [2]

task scaling strategies
Task-scaling Strategies
  • Application scaling (AS):
    • Used for workloads that are difficult to power manage
      • Audio and video processing
      • Begin processing next sample immediately
    • Operate a lower operating point
    • Increases to higher operating point when it begins to fall behind.

Rajami and Brock [2]

results of dpm
Results of DPM
  • IS: Idle Scaling LS: Load Scaling AS: Application Scaling
  • Frame-Scaling (FS): perfect knowledge of processing requirements of video frame

Rajami and Brock [2]

too many low power states
Too Many Low Power States
  • Disadvantages:
    • Confusion
    • Wrong low power state
  • Solution:
    • Minimize the number of state
    • Decrease complexity

Image: http://kunaljanu.files.wordpress.com/2009/02/ ist2_1457667confusion-1.jpg

sources of power consumption
Sources of Power Consumption
  • Microcontroller
  • Bus architecture
    • On chip communication
    • External communication
  • Memory hierarchy
  • Peripherals

Rajami and Brock [2]

communication architectures
Communication Architectures
  • Advanced Microcontroller Bus Architecture
    • ARM bus protocol for system-on-a-chip (SOC)
    • Advanced High Performance Bus (AHB)
      • Pipelined
      • Memory mapped
      • Up to 16 masters, 16 slaves
    • Advanced Peripheral Bus (APB)
      • Non pipelined
      • Single master, up to 16 peripherals

Rajami and Brock [2]

amba on chip bus
AMBA On-chip Bus

Rajami and Brock [2]

power profiling
Power Profiling
  • 86% power consumed by logic
  • 14% power consumed by bus lines

Rajami and Brock [2]

power reduction techniques
Power Reduction Techniques
  • Power Management
    • Shut down bus interfaces to idle slaves
  • Bus Encoding
    • Reduces # of line transitions, but not bus transactions
  • Traffic Sequencing
    • Reduce multiple masters interleaving bus access

Rajami and Brock [2]

power reduction techniques1
Power Reduction Techniques
  • No technique achieves large saving alone

Rajami and Brock [2]

power vs energy
Power vs Energy
  • Power is amount of energy over an amount of time (Watts = Joules / second)
  • Battery provides finite amount of energy
    • Goal: minimize energy use, not just power
  • In mobile systems we care about energy
    • Budget energy to prolong battery life

Rajami and Brock [2]

static system optimization
Static System Optimization
  • Compiler techniques
    • Instruction energy consumption profiling
      • Done empirically
    • Instruction reordering
      • Without affecting correctness
      • Improve register utilization
      • Reduce memory accesses
      • Reduce pipeline stalls
static system optimization1
Static System Optimization
  • Code Compression
    • Post compilation static optimization
    • Reduces storage size of instructions
    • Can have a large impact
    • Requires complex design space exploration
    • Goal for mobile system: reduce power consumption while preserving performance
code compression challenges
Code Compression Challenges
  • Random access decompression
    • Defining decodable block beginnings
    • Jump to new locations in program without decoding all blocks between
  • Solutions
    • Begin compressed blocks on byte boundaries
    • Store translation table
      • More efficient the compression, larger the table
    • Recalculate branch offsets to compressed addresses
code compression requirements
Code Compression Requirements
  • Additional hardware
    • Additional memory to store table
    • Decompression unit
  • Design decisions
    • Table generation/lookup
    • Compression technique
code compression implementation
Code Compression Implementation
  • SPARC ISA
  • Optimize consumption of complete SOC
  • Multiple iterations on binary
  • Instructions split into 4 categories
    • Group 1: immediate instructions (code = 0)
    • Group 2: branch instructions (code = 11)
    • Group 3: dictionary instructions (code = 100)
    • Group 4: uncompressed instr (code = 101)
diagram

Update branch offsets

Phase 4

Branch compression

Phase 3

Immediate compression

Phase 2

Markov model

Phase 1

Diagram

Optimized Binary

Compiled

Binary

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as a result
As a Result…
  • Bus Compaction
    • Instructions transmitted no longer require entire bus
    • Use the extra lines to transmit the next compressed instruction
decompression architecture
Decompression Architecture
  • Pre-Cache
    • Decompression engine between memory/cache
  • Post-Cache
    • Decompression engine between cache/cpu
simulation
Simulation
  • Full SOC simulation
  • 7 sample apps run
results1
Results
  • Net energy saving observed
    • 22-82% power savings from code compression
    • What about additional hardware?
  • Bonus
    • Increased performance
    • Reduced area
verdict
Verdict
  • Static power optimization
    • Potentially large payoff for little preprocessing
  • Still more sources of consumption
    • We’ve observed SOC savings
    • What about peripherals?
energy budget
Energy Budget

Voice Call

SMS

Energy

Budget

Emails

Pictures

localization

energy budget localization
Energy Budget: Localization
  • How much of the energy budget should be given to localization?
    • Depends on the user
  • Grant increase allotment when localization is a higher priority
localizations methods

1

2

3

  • GSM
  • Lower accuracy
  • Lower power requirement
  • GPS
  • Very accurate
  • Power Hungry
  • WiFi
  • Mod. Accurate
  • Mod. Power requirement
Localizations Methods
power vs precision
Power vs. Precision

Localization

Power:

amount of energy required by peripheral in order to determine location

Precision:

Accuracy of the device used for localization

Constandache, Gaonkar, Sayler, Choudhury, Cox [3]

power consumption
Power Consumption
  • 30 Second sampling intervals
  • Power Consumption:
    • GPS: High baseline
    • WiFi: Low baseline with high spikes
    • GSM: Low baseline with varying spikes

Constandache, Gaonkar, Sayler, Choudhury, Cox [3]

power consumption1
Power Consumption
  • 30 Second sampling intervals
  • Results:
    • GPS: increased baseline

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localization accuracy
Localization Accuracy
  • Accuracy varied based on location
  • ALE: Average Location Error
  • Wifi and GSM oversampled

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ThemeGallery is a Design Digital Content & Contents mall developed by Guild Design Inc.

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diagram4

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Diagram

Text

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cycle diagram

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B

A

C

Microcontroller

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Sources

D

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2004

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progress diagram

Phase 1

Phase 2

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Progress Diagram

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diagram6
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Company History

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slide53
Map

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slide56

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