1 / 98

Digitally Controlled Power Supplies Introduction and design considerations

Digitally Controlled Power Supplies Introduction and design considerations. David Figoli Shamim Choudhury Digital Power Systems Texas Instruments Houston. Agenda. Technology Overview Hardware Software Control Theory. Scope of Digital Power Control. Telecom infrastructure

quasim
Download Presentation

Digitally Controlled Power Supplies Introduction and design considerations

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Digitally Controlled Power Supplies Introduction and design considerations David Figoli Shamim Choudhury Digital Power Systems Texas Instruments Houston

  2. Agenda • Technology Overview • Hardware • Software • Control Theory

  3. Scope of Digital Power Control • Telecom infrastructure • Base stations • Servers • Routers • Workstations • Industrial 400KHz ~ 1MHz 200KHz ~ 500KHz 100KHz ~ 200KHz

  4. Full Digital control system • Resolution • Topology support • “speed” 0110101100 1011011101 0010100111 DAC Digital Controller ADC “Plant” • MIPS “engine” • “C” (HLL) Efficiency • Data size (e.g. 16/32 bits?) • Resolution • Linearity / Accuracy • Speed (sampling rate)

  5. Time sampled systems

  6. Time Division Multiplexing – TDM (1/2)

  7. Time Division Multiplexing – TDM (2/2)

  8. 10Kw RAM 64Kw Flash + Emulated EE 4Kw Boot ROM XINTF Memory Bus EPWM x 6 CAN x 2 I2C ADC (12b) APWM x 4 SCI x 2 SPI x 4 100 MIPs C28xTM 32-bit DSP Peripheral Bus RMW Atomic ALU 32x32-bitMultiplier 32-bitTimers (3) 32-bit Register File Real-Time JTAG GPIO F280x - Digital Controller engine 6 timers  6 phases 12 PWMs  12 x Vout 4 of 12  HiRes PWM F280x Code security 4 timers  4 phases 4 PWMs  4 x Vout Interrupt Management 12 bit @ 12.5 MSPs PMBus

  9. PWM resources – F2808 10 timebases  10 independent freq.  10 phase Interleaved ( 36o phase offset ) 16 independent duty  16 Vout rails  10 independent freq.  4 with HiRes PWM Combinations  1x6phase / 4xSingle  2x3phase / 4xSingle  3x3phase / 1xSingle  3x3phase / 7xSingle* Note: F2809 will have 6 HRPWM

  10. Example: AC/DC – Rectifier Control • 1000W • F280x DSP based • 2 phase interleaved PFC • Phase shifted ZVS-FB • 200 KHz PWM (DC/DC) • 100 KHz PWM (PFC)

  11. Example: DC/DC Control

  12. A closer look .... 0110101100 1011011101 0010100111 • Resolution • Topology support DAC Digital Controller ADC “Plant” • MIPS “engine” • “C” Efficiency • Data size (e.g. 32 bits) • Resolution • Linearity / Accuracy • Speed (sampling rate)

  13. Processor consideration # Inst. vs Algorithm # Instructions vs PWM MIPS = Million Instruction Per Second

  14. CPU Performance requirements (1/2) • ISR Bandwidth utilization = TISR / TSAMPLE * 100%

  15. CPU Performance requirements (2/2) ISR Utilization for PWM frequency vs # Control loops Note: Entries in red require more than 100% and are not possible.

  16. ADC consideration ADC ADC utilization - # Channels (“Loops”) vs PWM freq. ( Note: 12.5 MSPS = 80 nS conversion )

  17. Example: ADC capability of F280x F280x – on chip ADC • 12 bit resolution / Pipeline architecture / Dual S/H • up to 12.5 MSPS / 80 nS conversion • 16 Analog channels • Programmable S/H apperture window • Start of Conversion (SOC) trigger via PWM timer • SNR = 67dB / THD = -74dB • DNL = +/- 1LSB, INL = +/- 1.5LSB, Offset = +/- 4LSB A D C

  18. PWM consideration DAC VSTEP TSysclk PWM resolution = Log2 ( TPWM / TSysClk ) 280x PWM

  19. Example: Regular vs High Res PWM 280x System Clock = 100 MHz PWM freq = 10 MHz Period = 10 clocks (i.e. 10 step resolution) Voltage resolution = 3.3V/10 = ~300mV Hi-Resolution PWM 300 mV Conventional PWM Voltage output shown as ramp function

  20. Vo levels (DPWM duty ratio steps) ADC levels error bins Volt +0010 ΔVs ΔVc +0001 ΔVs Vref 0000 ΔVc -0001 steady state output, limit cycle time Vo levels (DPWM duty ratio steps) ADC levels error bins Volt ΔVc +0010 ΔVs +0001 ΔVs Vref 0000 -0001 steady state output, no limit cycle time Limit Cycle Oscillation in Digital Power Converter

  21. Example: Closed loop HiRes PWM Regular (10nS) PWM HiRes (150pS) PWM

  22. Example: HiRes PWM – a closer look Non-HiRes HiRes

  23. Resolution loss - low duty utilization Resolution Loss in bits

  24. Hardware ...

  25. AC/DC - Rectifier • 1000W • F280x DSP based • 2 phase interleaved PFC • Phase shifted ZVS-FB • 200 KHz PWM (DC/DC) • 100 KHz PWM (PFC)

  26. Common & Diff. mode filter In-Rush Relay

  27. Interleaved Boost Converter IPFC PWM PFC IPHA & B

  28. Phase Shifted Full Bridge IDCDC PWM PSFB VOUT

  29. Signal Conditioning / DSP Interface F280x (partial view)

  30. F280x “Life support”

  31. BH2808 Contoller board F2808 DSP controller board • “battle hardened” design for harsh electrical environments • DIMM 100 pin format • Isolated SCI Interface • JTAG port for real-time debug • Dimensions – 1.4” x 3.5” (35 x 89 mm)

  32. Actual System hardware PFC Phase 2 PFC Phase 1 FET+Diode Bridge Rect. Con. Inductor 1 Inductor 2 In-rush relay DC bus Caps (900uF) Full Bridge Left-leg Full Bridge Right-leg Res. Ind. Common / Diff mode chokes Output diodes Isolation transformer Output diodes Output Ind. DSP controller Output Caps Voltage Feedback opto

  33. Multi-phase / Output DC/DC

  34. DC/DC ...more details

  35. The Power stage

  36. UCD7230 gate driver

  37. 6 ch power EVM + 2808 ezDSP

  38. Software ...

  39. Software Framework for a Digital Controller “infrastructure which supports the application” Considerations • How many ISRs (Interrupt Service Routines) • Are ISRs Synchronous or Asynchronous ? • CPU % utilization balance between ISRs and Background (BG) • High level language (HLL), e.g. “C/C++”, Assembly ?, or both ? • Need to employ an Operating system ? • Interrupt driven Communications ?

  40. The simple “ISR / BG” Framework (1/2) “keep it simple” • 2 Loops only • ISR code has highest priority • ISR Synchronous to PWM switching • ISR incurs entry/exit overhead • BG runs only during ISR “idle time”

  41. The simple “ISR / BG” Framework (2/2) • Can Time slice the ISR for simple synchronous multi-task scheduling • In a practical system BG needs approx 15~20% of CPU bandwidth • If CPU timing is “tight” may consider using a H/W accelerated controller

  42. Single ISR / BG loop example

  43. Time Sliced ISR – Practical example (1/2)

  44. Time Sliced ISR – Practical example (2/2)

  45. Hardware Accelerated Controllers (1/2) Accelerated Controller Note: CLA = Control Law Accelerator Non-Accelerated Controller

  46. Hardware Accelerated Controllers (2/2) UCD9110 example with CLA Note: a 3 execution thread system. F2801 example #1 Time-sliced ISR for slow loops C2, C3 F2801 example #2 BG managed slow loops C2, C3

  47. Code development strategy • Modularity - blocks with well defined inputs / outputs (“cause and effect”) • Multiple Instancing - use of same function (module) many times • Peripheral (h/w) drivers - separate core code from peripheral code • Re-useable / Re-targetable - maximize return on investment • Efficiency & high performance - code execution in minimal time

  48. Software Library approach

  49. Modular s/w architecture “Signal Net” based module connectivity Initialization time (“C”) Run time (ASM macros) ; Execute the code f1 f2 f3 f4 f5 // pointer & Net declarations Int *In1A, *In1B, *Out1, *In2A,... Int Net1, Net2, Net3, Net4,... // “connect” the modules In1A=&Net1; In1B=&Net2; Out1=&Net5; In2A=&Net3; Out2=&Net6; In3A=&Net4; Out3=&Net7; In4A=&Net5; In4B=&Net6; In4C=&Net7; Out4=&Net8; In5A=&Net7; Out5=&Net9;

  50. PFC (2PHIL) Software control flow

More Related