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Group 1. Ted Merchant Matt Wojcik Evan Owski Matt Robben EECS 362 1/10/2008. Move. The move commands are used to move data from on register type to another register type. There are three types of moves: Move Between GPR and Special Registers (Interrupt Address Register)
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Group 1 Ted Merchant Matt Wojcik Evan Owski Matt Robben EECS 362 1/10/2008
Move • The move commands are used to move data from on register type to another register type. • There are three types of moves: • Move Between GPR and Special Registers (Interrupt Address Register) • GPR to a SR MOVI2S src • SR to a GPR MOVS2I dst • Move between floating point registers, both 32 and 64 bit precision • Single FPR to single FPR MOVF dst, src • Double FPR to double FOR MOVD dst, src • All moves between double precision FPR copy a even/odd pair of single precision FPR. The dst and src arguments are the even registers • Move between GPR and FPR • Single FPR to GPR MOVFP2I dst, src • GPR to single FPR MOVI2FP dst, src • To move between a double FPR to GPR move the contents of each half of the double FPR to two different GPRs
Store • Store is an I-Type instruction. • The store instruction is used to place data from a register into memory • The memory address is created by adding a 16-bit offset to the value in a general-purpose register • The memory access must be aligned on a byte, half-word, or word boundary • There are two types of store instructions: • Store general-purpose registers • Store floating-point registers
Store • Integer store instructions: • Store byte SB offset(rs),rd • Store half-word SH offset(rs),rd • Store word SW offset(rs),rd • May use any general-purpose register as the source of data. • Floating-point store instructions: • Single precision SF offset(rs),rd • Double precision SD offset(rs),rd • SF may use any floating-point register • SD may use any even/odd pair of floating point registers.
Jump • The four available jump instructions actually span both I-type and J-type categories • There are four jump-related instructions, two J-type and two I-type J-Type Instructions: bits 0-5 are the opcode, 6-31 a specific address • Jump (J) – unconditional jump directly to the address specified in bits 6-31 • Jump and link (JAL) – same as J, but the current PC+4 is stored into $ra I-Type Instructions: 0-5 opcode, 6-10 address, 11-15 unused, 16-31 unused • Jump register (JR) - unconditional jump to address in Rs1 • Jump and link register (JALR) – same as JR, but saves PC+4 into $ra
Jump Uses • Jump and link / jump register instructions used for procedure entry and exit SAMPLE ASM: ld $a0,100($a2) //load parameters jal fact //jump and save PC+4 to $ra … //next PC fact: … //do stuff addi $sp,$sp,4 //clean up stack jr $ra //jump to old PC+4
Reusable Components • ALU – with modification • Bit shifters & extenders (2, 5, & 32 bit) • MUXes
Pipelining Complications • Obvious • Data dependencies & forwarding • Branch prediction • Stalls & flushes • Tough to build and debug • Not so obvious • Properly updating & saving PC data requires more storage or more complex control / datapath • Intricacy - design flaws are very difficult to fix