Mid-Term Presentation Fast Ethernet Card with FPGA Project num. 0622 Students: Alex Shpiner - PowerPoint PPT Presentation

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Mid-Term Presentation Fast Ethernet Card with FPGA Project num. 0622 Students: Alex Shpiner
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Mid-Term Presentation Fast Ethernet Card with FPGA Project num. 0622 Students: Alex Shpiner

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  1. 12.5.03 הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל המעבדה למערכות סיפרתיות מהירות Mid-Term Presentation Fast Ethernet Card with FPGA Project num. 0622 Students:Alex Shpiner Eyal Azran Supervisor:Boaz Mizrahi

  2. Project Description • Programming FPGA device on the network card which connects PCI Bus with Fast Ethernet network. • Transmitting and receiving packages over the network. • Developing algorithm for arbitration between transmitting and receiving packages. • Allowing future development of the device, such as adding UTOPIA port or manipulation of the transmitted packages.

  3. General scheme of the card: MAC PHY PLX

  4. Scheme of the blocks in the FPGA: PHY GNR C I F MCF PCI Bridge MAC TRN Shared bus ARB RCV

  5. Path of the packages over the card: FPGA TRN MAC + PHY FIFO E T H E R N E T CIF P C I FIFO PCI Bridge Shared bus ARB FIFO RCV FIFO

  6. Transmitting rates and FIFO sizes: 2kbytes 128 bytes P C I E T H E R N E T FPGA TRN FIFO MAC TRN FIFO FPGA RCV FIFO MAC RCV FIFO 100 Mbit/sec 1 Gbit/sec 1 Gbit/sec

  7. Quantum calculation Time to fill MAC FIFO = 128X8bit/100 Mbitps = 10240 ns Clock cycle = 1/33Mhz = 31 ns Cycles to fill MAC FIFO = 10240/31 = 331 cycles FPGA-MAC transfer rate = 33Mhz X 32bit = 1Gbit/s Time to flush MAC FIFO = 128X8bit/32 bits = 32 cycles => Quantum = 32 cycles

  8. Focus on the arbitration algorithm TRN ARB RCV request request done done grant grant

  9. Arbitration algorithm • Algorithm is based on round robin technique. • Each entity will have specified quantum time. • Early finish – by raising DONE signal. • Receiver has higher priority than the transmitter. • FIFO overflow control by interrupts. • Arbitration with PCI bus and devices configuration is controlled by sending specific address to the CIF. • Wide range of addresses will be used for future expansions.

  10. 21/05/03 - Simulate and synthesize RCV unit. 28/05/03 - Test and debug RCV unit. 04/06/03 - Write ARB code. 11/06/03 - Simulate and debug ARB. 18/06/03 - Connecting ARB with the components. 25/06/03 - Simulate and debug whole system. Final Moed A Exams. 30/07/03 - Final testing on the hardware. 06/08/03 - Finalize project book. Schedule