UNIT-V VHDL Synthesis: VHDL Synthesis, Circuit Design

1. UNIT-V VHDL Synthesis: VHDL Synthesis, Circuit Design Flow, Circuit Synthesis, Simulation, Layout,Design capture tools, Design Verification Tools. Test and Testability: Fault-modelling and simulation, test generation, design for testability, Built-inself-test.

2. Circuit Design • Flow:

4. Simulation is the process of using a simulation software (simulator) to verify the functional correctness of a digital design that is modeled using a HDL (hardware description language) like VHDL and Verilog. Types of Simulations: • Behavioral simulation • Functional simulation • Gate-level simulation • Switch-level simulation • Transistor-level or circuit-level simulation .

5. Synthesis is a process in which a design behavior that is modeled using a HDL is translated into an implementation consisting of logic gates. This is done by a synthesis tool which is another software program

6. Synthesis – The Process of converting one representation of a circuit (source representation) to another functionally equivalent representation (target representation). Types: 1. Circuit Synthesis 2. Logic Synthesis 3. Architecture Synthesis

7. Structural Behavioral Synthesis Physical Design Physical

8. Structural Behavioral Processor Memory Bus Algorithm Flowchart PCBs MCMs(Multichip module) Physical

9. Circuit Synthesis • Synthesis is the process to convert a circuit description written in HDL to gate level description. module my_module input i1 , …. ; output out1 , …. ; reg …. wire … always @(…..) nand2 n1 (…) Dff d1 (..)

10. Logic Synthesis • Convert from logic equations to gate-level netlists (assume combinational logic). • Maximize speed • Minimize area, power a’bc + abc + d bc + d b b c c d d

12. Taxonomy of Synthesis Tasks

13. Design Capture Tools: HDL Design Schematic Design Layout Design Floor Planning Chip Composition

14. HDL Design: In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits

16. Schematic Design:

19. Layout Design:

22. Floor planning must take into account blocks of varying function , size, shape. Must design: •space allocation •signal routing •power supply routing •clock distribution Floor planning

26. Chip Composition:

28. Design Verification Tools:

30. Simulation Timing Verifiers Network Isomorphism Netlist Comparison Layout Extraction Back Annotation Design rule Verification Pattern generation

31. Simulation: Simulation is the process of using a simulation software (simulator) to verify the functional correctness of a digital design that is modeled using a HDL (hardware description language) like Verilog Circuit level Timing simulator Logic level Switch level

32. Timing Verifiers: Timing simulation is called post-route simulation because it confirms that your design is compatible with the timing and propagation delays that exist in a specific device.

33. Network Isomorphism: Network Isomorphism An electrical network may be represented by a graph where the vertices of the graph are devices such as MOS transistors, bipolar transistors, diodes, resistors, and capacitors. The arcs are the connections between devices. These are the electrical nodes in the circuit. Network Isomorphism is used to prove that two networks are equivalent and therefore and should function equivalently.This is used most often to prove that layout is equivalent to network extracted from schematic or HDL structural netlist.

34. Netlist Comparison The process of comparing two networks is commonly called netlist comparison.

35. Often want to iteratively improve design. Back annotation updates a more-abstract design with information from later design stages. •Example: annotate logic schematic with extracted parasitic Rs and Cs. Back annotation

36. Layout Extraction:

38. Design rule Verification:

41. Pattern generation:

44. Test and Testability

46. Fault-modelling: Fault (Malfunction)is defined as the physical defect of one (or) more components (or) the connections between the components in the given circuit. Faults can be occur in many ways 1) General approach 2) Logical approach

47. 1) General approach a) Permanent faults b)Temporary faults i) Transient faults ii) Intermediate faults

48. Permanent faults: • It is also called hard fault. • A fault that is occurred due to breaking of a component • or wire is called as permanent fault. • This fault is stay with device uptoreplacementof breaking component. Temporary faults: This kind of fault may occur at certain time intervals. i) Transient faults: The fault which is occurred due to some power supply fluctuations. ii) Intermediate faults: This kind of fault is occurred due to the component misbehaviour sometimes this turns into permanent faults.

49. 2) Logical approach a) Logical faults i) Stuck at faults a) Stuck at ‘0’ fault b) Stuck at ‘1’ fault ii) Bridging faults a) AND type b) OR type iii) Cross point faults b) Parametric faults

50. Logical faults: This kind of fault change the boolean function obtained by the given circuit A Actually Y=AB. B Y but Y=A+B