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Nanocomputer Systems Engineering

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  1. Nanocomputer Systems Engineering The full paper is available at:http://www.cise.ufl.edu/research/revcomp/theory/NanoTech2003/Frank-NanoTech-2003.doc, .ps. Laying the Key Methodological Foundations for the Design of 21st-Century Computer Technology Michael P. Frank CISE & ECE DepartmentsUniversity of Florida<mpf@cise.ufl.edu>

  2. Cost-Efficiency:The Key Figure of Merit • All practical engineering design-optimization can ultimately be reduced to maximization of generalized, system-level cost-efficiency. • Given appropriate models of cost “$”. • Definition of Cost-Efficiency %$ a Process: %$ :≡$min/$actual • Maximize %$ by minimizing $actual • This is valid even when $min is unknown

  3. Important Cost Categories in Computing Focus oftraditionaltheories ofso-called“computationalcomplexity” • Hardware-Proportional Costs: • Initial Manufacturing Cost • Time-Proportional Costs: • Inconvenience to User Waiting for Result • (HardwareTime)-Proportional Costs: • Lifetime-Amortized Manufacturing Cost • Maintenance & Operation Costs • Opportunity Costs • Energy-Proportional Costs: • Adiabatic Losses • Non-adiabatic Losses From Bit Erasure • Note: These may both vary independently of (HWTime)! These costsneed to beincluded also in practicaltheoreticalmodels ofnanocomputing

  4. Two-Pass System Optimization • A general methodology for the interdisciplinary optimization of the design of complex systems. • Performance characteristicsof system are expressed asfunctions of system’s design parameters, & subsystems’ own characteristics. • Then, optimize designparameters from top downto maximize overall system-wide cost-efficiency. Top-levelsystems design High-levelsubsystems Characterize cost-efficiency from bottom upwards Optimize design parameters from top downwards. Mid-levelcomponents Lowest-leveldesign elements

  5. Logic Devices Technology Scaling Interconnections Synchronization Processor Architecture Capacity Scaling Energy Transfer Programming Error Handling Performance Cost Computer Modeling Areas An Optimal, Physically Realistic Model of Compu-ting Must Accurately Address All these Areas!


  6. Fundamental Physical Constraints on Computing ImpliedUniversal Facts Affected Quantities in Information Processing Thoroughly ConfirmedPhysical Theories Speed-of-LightLimit Communications Latency Theory ofRelativity Information Capacity UncertaintyPrinciple Information Bandwidth Definitionof Energy Memory Access Times QuantumTheory Reversibility 2nd Law ofThermodynamics Processing Rate Adiabatic Theorem Energy Loss per Operation Gravity

  7. Landauer’s Principle (1961):Bit Erasure Creates Entropy Before bit erasure: After bit erasure: s0 0 s0’’ 0 Nstates … … … sN-1 0 0 sN-1’’ Unitary(1-1)evolution 2Nstates s’0 sN’’ 1 0 Increase in entropy: S = log 2 = k ln 2 Energy lost to heat:ST = kT ln 2 Nstates … … … 0 s’N-1 s2N-1’’ 1

  8. Reversible / Adiabatic Chips Designed @ MIT, 1995-1999 By the author and other then-students in the MIT Reversible Computing group,under AI/LCS lab faculty members Tom Knight and Norm Margolus.

  9. Example Application of Our Engineering Methodology • A research question to be answered: • As nanocomputing technology advances,will reversible computing become very cost-effective, and if so, when? • We applied our methodology as follows: • Made Realistic Model (Obeying Constraints) • Optimized Cost-Efficiency in the Model • Swept Model Parameters over Future Years

  10. Important Factors Included in Our Model • Entropic cost of irreversibility • Algorithmic overheads of reversible logic • Adiabatic speed vs. energy-loss tradeoff • Optimized degree of reversibility • Limited quality factors of real devices • Communications latencies in parallel algorithms • Realistic heat flux constraints

  11. Technology-Independent Model of Nanoscale Logic Devices Id– Bits of internal logical state information per nano-device Siop– Entropy generated per irreversible nano-device operation tic– Time per device cycle (irreversible case) Sd,t– Entropy generated per device per unit time (standby rate, from leakage/decay) Srop,f– Entropy generated per reversible op per unit frequency d– Length (pitch) between neighboring nanodevices SA,t– Entropy flux per unit area per unit time

  12. Technological TrendAssumptions Entropy generatedper irreversible bittransition, nats Absolute thermodynamiclower limit! Minimum pitch (separation between centers of adjacent bit-devices), meters. Nanometer pitch limit Minimum time perirreversible bit-devicetransition, secs. Example quantum limit Minimum cost perbit-device, US$.

  13. Fixed TechnologyAssumptions • Total cost of manufacture: US$1,000.00 • User will pay this for a high-performance desktop CPU. • Expected lifetime of hardware: 3 years • After which obsolescence sets in. • Total power limit: 100 Watts • Any more would burn up your lap. Ouch! • Power flux limit: 100 Watts per square centimeter • Approximate limit of air-cooling capabilities • Standby entropy generation rate: 1,000 nat/s/device • Arbitrarily chosen, but achievable

  14. Cost-Efficiency Benefits of Reversible Computing Scenario: $1,000/3-years, 100-Watt conventional computer, vs. reversible computers w. same capacity. ~100,000× ~1,000× Best-case reversible computing Bit-operations per US dollar Worst-case reversible computing Conventional irreversible computing All curves would →0 if leakage not reduced.

  15. More Recent Work Optimizing device size tominimize entropy generation

  16. Minimizing Entropy Generationin Field-Effect Nano-devices

  17. Lower Limit to Entropy Generation Per Bit-Operation • Scaling withdevice’s quantum“quality” factor q. • The optimal redundancyfactor scales as: 1.1248(ln q) • The minimumentropy gener-ation scales as:q −0.9039

  18. Conclusions • We have developed an integrated and principled methodology for analysis of nanocomputer systems engineering. • Techniques such as this are needed to address difficult but important questions. • E.g., the cost-efficiency of reversible computing. • Preliminary results indicate that reversible computing offers extreme cost-efficiency advantages for future nanocomputing. • Even when taking its overheads into account!