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FPGA-Based SAT Solver Design and Implementation

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This project focuses on the development of a hardware-based SAT solver utilizing FPGA technology. The core objective is to evaluate Boolean satisfiability problems (SAT), where we determine if there exists an assignment of values to variables such that a given Boolean formula evaluates to true. The project involves implementing DIMACS CNF instances in VHDL, an efficient process leveraging logic elements (LUTs) in FPGAs. Initiated in Winter 2012, this semester-long project aims to construct a SAT solver that effectively handles CNF formats, showcasing the application of FPGA technology in solving complex logical problems.

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FPGA-Based SAT Solver Design and Implementation

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  1. FPGA Based SAT Solver Saleem Sabbagh & Najeeb Darawshy Supervisors: Mony Orbach, Technion & Ilia Averbouch, IBM Project Characterization Started at: Winter 2012 Duration: Semester

  2. What is sat • Boolean Satisfiability Problem • Given a Boolean propositional formula, does there exist assignment of values such that the formula becomes true? • e.g., given the formula f=(x1 ˅x2 ˅-x4) ˄ (x4) ˄ (x2 ˅ -x3) are there values of x1,x2,x3,x4 that produce f=‘1’

  3. cnf • Conjunctive Normal Form • In Boolean Logic, a formula is in CNF if it presented as a conjunction of clauses. • e.g., DIMACS CNF format: c Example CNF format file c p cnf 4 3 1 3 -4 0 4 0 2 -3 0

  4. Description • Hardware based SAT Solver • Implementing DIMACS cnf instances into FPGA

  5. Project Goals

  6. CNF to vhdl example Example.vhdl Example.cnf c Example CNF format filec p cnf 4 31 3 -4 04 02 -3 0 entity SAT is port( x1,x2,x3,x4: in std_logic; F: out std_logic ); end OR_ent; architecture SAT_arc of SAT is begin F <= (x1 or x3 or (not x4) and (x4) and (x2 or (not x3)); end SAT_arc;

  7. Software Environment

  8. Technology • LUT Logic Elements • LUT is a function generator that can implement any function of four variables. • Each clause will be implemented on one LUT therefor we 4000 clauses occupy 8000 LUTs (=LEs) • Random Generator (32 Bit output) • Seed * Constant + Constant • Each variable will receive a random bit, therefor 500 variables 64 x 16 = 1024 LUTs (=LEs)

  9. Technical Overview

  10. Flow diagram Programmable File Circuit Description as VHDL CNF Instances Synthesis Conversion Device Programmer FPGA Running SAT Solver PC DE2 Analysis and Timing Report

  11. Gantt chart

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