Comp541 hierarchical design verilog
1 / 52

COMP541 Hierarchical Design & Verilog - PowerPoint PPT Presentation

  • Updated On :

COMP541 Hierarchical Design & Verilog. Montek Singh Jan 28, 2010. Topics. Hierarchical Design Verilog Primer. Design Hierarchy. Just like with large program, to design a large chip need hierarchy Divide and Conquer To create, test, and also to understand Block is equivalent to object.

Related searches for COMP541 Hierarchical Design & Verilog

I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
Download Presentation

PowerPoint Slideshow about 'COMP541 Hierarchical Design & Verilog' - udell

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Comp541 hierarchical design verilog l.jpg

COMP541Hierarchical Design & Verilog

Montek Singh

Jan 28, 2010

Topics l.jpg

  • Hierarchical Design

  • Verilog Primer

Design hierarchy l.jpg
Design Hierarchy

  • Just like with large program, to design a large chip need hierarchy

  • Divide and Conquer

    • To create, test, and also to understand

  • Block is equivalent to object

Example l.jpg

  • 9-input odd func (parity for byte)

  • Block for schematic is box with labels

Design broken into modules l.jpg
Design Broken Into Modules

Use 3-input odd functions

Use nand to implement xor l.jpg
Use NAND to Implement XOR

  • In case there’s no XOR, for example

Components in design l.jpg
Components in Design

  • RHS shows what must be designed

Reuse is common l.jpg
Reuse is Common

  • Certainly forced because of availability of parts (chips)

  • Also the design cycle was very long

  • Now more flexibility with programmable logic

    • But still reuse from libraries or intellectual property (IP)

    • Example: buy a PCI design

    • Open source, see

  • Note the many logic blocks available in Xilinx library

Flow of cad system l.jpg
Flow of CAD System

Netlist is description of connections

Replaces Generic Gates with ones available in Technology Library

Generic Gates

Technology mapping l.jpg
Technology Mapping

  • Full custom

    • Pixel-Planes chips (machines in lobby)

    • Memories, CPUs, etc

  • Standard cell

    • Library of cells

    • Engineer determined interconnection

  • Gate arrays

    • Small circuits with interconnect

Hierarchy example 4 bit equality l.jpg
Hierarchy Example – 4-bit Equality

  • Input: 2 vectors A(3:0) and B(3:0)

  • Output: One bit, E, which is 1 if A and B are bitwise equal, 0 otherwise

Design l.jpg

  • Hierarchical design seems a good approach

  • One module/bit

  • Final module for E

Design for mx module l.jpg
Design for MX module

  • Logic function is

    • I’d call this “not E”…

    • Can implement as

Design for me module l.jpg
Design for ME module

  • Final E is 1 only if all intermediate values are 0

  • So

  • And a design is

Hierarchical verilog l.jpg
Hierarchical Verilog

  • We already saw example of instantiation when we used AND and OR gates

  • Just use module name and an identifier for the particular instance

Vector of wires bus l.jpg
Vector of Wires (Bus)

  • Denotes a set of wires

    input [1:0] S;

  • Syntax is [a: b] where a is high-order

    • So this could be “[0:1] S”

    • Order will matter when we make assignments with values bigger than one bit

    • Or when we connect sets of wires


Slide19 l.jpg

module mx(A, B, E);

input A, B;

output E;

assign E = (~A & B) | (A & ~B);


Slide20 l.jpg

module me(E, Ei);

input [3:0] Ei;

output E;

assign E = ~(Ei[0] | Ei[1] | Ei[2] | Ei[3]);


Top level l.jpg
Top Level

module top(A, B, E);

input [3:0] A;

input [3:0] B;

output E;

wire [3:0] Ei;

mx m0(A[0], B[0], Ei[0]);

mx m1(A[1], B[1], Ei[1]);

mx m2(A[2], B[2], Ei[2]);

mx m3(A[3], B[3], Ei[3]);

me me0(E, Ei);


Integrated circuit l.jpg
Integrated Circuit

  • Known as IC or chip

  • Silicon containing circuit

    • Later in semester we’ll examine design and construction

    • Maybe processes

  • Packaged in ceramic or plastic

    • From 4-6 pins to hundreds

  • Pins wired to pads on chip

Levels of integration l.jpg
Levels of Integration

  • SSI

    • Individual gates

  • MSI

    • Things like counters, single-block adders, etc.

    • Like stuff we’ll be doing next

  • LSI

  • VLSI

    • Larger circuits, like the FPGA, Pentium, etc.

Logic families l.jpg
Logic Families

  • RTL, DTL earliest

  • TTL was used 70s, 80s

    • Still available and used occasionally

    • 7400 series logic, refined over generations

  • CMOS

    • Was low speed, low noise

    • Now fast and is most common

  • BiCMOS and GaAs

    • Speed

Catalogs l.jpg

  • Catalog pages describe chips

  • Look at

  • Specifications

    • Pinouts

    • Packages/Dimensions

    • Electrical characteristics

Electrical characteristics l.jpg
Electrical Characteristics

  • Fan in

    • max number of inputs to a gate

  • Fan out

    • how many standard loads it can drive (load usually 1)

  • Voltage

    • often 1V, 1.2V, 1.5V, 1.8V, 3.3V or 5V are common

  • Noise margin

    • how much electrical noise it can tolerate

  • Power dissipation

    • how much power chip needs

      • TTL high

      • Some CMOS low (but look at heat sink on a Pentium)

  • Propagation delay – already talked about it

Change topics to l.jpg
Change Topics to

  • Verilog

    • First a couple of syntax styles

    • Help you program more efficiently

  • Verilog test programs

Constants in verilog l.jpg
Constants in Verilog

  • Syntax


  • Radix can be d, b, h, or o (default d)

  • Examples

    assign Y = 10; // Decimal 10

    assign Y = ’b10; // Binary 10, decimal 2

    assign Y = ’h10; // Hex 10, decimal 16

    assign Y = 8’b0100_0011 // Underline ignored

  • Binary values can be 0, 1, or x

Conditional assignment l.jpg
Conditional Assignment

  • Equality test

    S == 2'b00

  • Assignment

    assign Y = (S == 2'b00)? 1’b0: 1’b1;

    • If true, assign 0 to Y

    • If false, assign 1 to Y

4 to 1 mux truth table ish l.jpg
4-to-1 Mux Truth Table-ish

module mux_4_to_1_dataflow(S, D, Y);

input [1:0] S;

input [3:0] D;

output Y;

assign Y = (S == 2'b00) ? D[0] :

(S == 2'b01) ? D[1] :

(S == 2'b10) ? D[2] :

(S == 2'b11) ? D[3] : 1'bx ;


Verilog for decision tree l.jpg
Verilog for Decision Tree

module mux_4_to_1_binary_decision(S, D, Y);

input [1:0] S;

input [3:0] D;

output Y;

assign Y = S[1] ? (S[0] ? D[3] : D[2]) :

(S[0] ? D[1] : D[0]) ;


Binary decisions l.jpg
Binary Decisions

  • If S[1] == 1, branch one way

    assign Y = S[1] ? (S[0] ? D[3] : D[2])

    • and decide Y = either D[2] or D[3] based on S[0]

  • Else

    : (S[0] ? D[1] : D[0]) ;

    • decide Y is either D[2] or D[3] based on S[0]

  • Notice that conditional test is for ‘1’ condition like in C

Instance port names l.jpg
Instance Port Names

  • Module

    module modp(output C, input A);

  • Ports referenced as

    modp i_name(conC, conA)

  • Also as

    modp i_name(.A(conA), .C(conC));

Parameter l.jpg

  • Can set constant

    • Like #define

      parameter SIZE = 16;

Verilog for simulation l.jpg
Verilog for Simulation

  • Code more convenient than the GUI testbench

    • Also more complex conditions

    • Can test for expected result

Slide37 l.jpg

  • Make Verilog Test Fixture

  • Will create a wrapper (a module)

    • Instantiating your circuit

    • It’ll be called UUT (unit under test)

  • You then add your test code

  • Example on next slides

Module and instance uut l.jpg
Module and Instance UUT

module syn_adder_for_example_v_tf();

// DATE: 21:22:20 01/25/2004

// ...Bunch of comments...


// Instantiate the UUT

syn_adder uut (









Slide39 l.jpg

  • It will create storage for the inputs to the UUT

    // Inputs

    reg [3:0] B;

    reg [3:0] A;

    reg C0;

  • We’ll talk more about reg next class

Wires for outputs l.jpg
Wires for Outputs

  • That specify bus sizes

    // Outputs

    wire [3:0] S;

    wire C4;

Begin end l.jpg

  • Verilog uses begin and end for block

  • instead of curly braces

Initial l.jpg

  • Initial statement runs when simulation begins



    B = 0;

    A = 0;

    C0 = 0;


Procedural assignment l.jpg
Procedural assignment

  • Why no “assign”?

  • Because it’s not a continuous assignment

  • Explain more next class when we look at storage/clocking

Initialize in default test file l.jpg
Initialize in Default Test File

  • There’s one in ISE generated file, but don’t think auto_init is defined

    // Initialize Inputs

    `ifdef auto_init

    initial begin

    B = 0;

    A = 0;

    C0 = 0;



What to add l.jpg
What to Add?

  • Need to make simulation time pass

  • Use # command for skipping time

  • Example (note no semicolon after #50)



    B = 0;

    #50 B = 1;


Slide46 l.jpg

  • Can use for loop in initial statement block



    for(i=0; i < 5; i = i + 1)


    #50 B = i;



Integers l.jpg

  • Can declare for loop control variables

    • Will not synthesize, as far as I know

      integer i;

      integer j;

  • Can copy to input regs

    • There may be problems with negative values

There are also l.jpg
There are also

  • While

  • Repeat

  • Forever

Timescale l.jpg

  • Need to tell simulator what time scale to use

  • Place at top of test fixture

    `timescale 1ns/10ps

System tasks l.jpg
System Tasks

  • Tasks for the simulator

  • $stop – end the simulation

  • $display – like C printf

  • $monitor – prints when arguments change (example next)

  • $time – Provides value of simulated time

Monitor l.jpg

// set up monitoring



$monitor($time, " A=%b ,B=%b\n", A, B);


// These statements conduct the actual test





Slide52 l.jpg

  • Sequential Circuits

  • We’ll put off the study of arithmetic circuits