Brief Introduction to Verilog

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Brief Introduction to Verilog Weiping Shi What is Verilog? It is a hardware description language Allows designers to quickly create and debug large scale designs Similar to C in syntax Verilog will be used to do design assignments in this course a sum b c_out_bar c_out

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### Brief Introduction to Verilog

Weiping Shi

What is Verilog?
• It is a hardware description language
• Allows designers to quickly create and debug large scale designs
• Similar to C in syntax
• Verilog will be used to do design assignments in this course

a

sum

b

c_out_bar

c_out

module Add_half (sum, c_out, a, b);

input a, b;

output sum, c_out;

wire c_out_bar;

xor (sum, a, b);

nand (c_out_bar, a, b);

not (c_out, c_out_bar);

endmodule

Module Hierarchy
• Modules can be instantiated within other modules
• Allows for simplicity and regularity in the design
Module Hierarchy Example

module Add_half ( sum, c_out, a, b );

input a, b;

output sum, c_out;

wire c_out_bar;

xor (sum, a, b);

nand (c_out_bar, a, b);

not (c_out, c_out_bar);

endmodule

Module Add_full ( sum, c_out, a, b, c_in ); // parent module

input a, b, c_in;

output c_out, sum;

wire w1, w2, w3;

Add_half M1 ( w1, w2, a, b );

Add_half M2 ( sum, w3, w1, c_in ); // child module

or ( c_out, w2, w3 ); // primitive instantiation

endmodule

module Add_half ( sum, c_out, a, b );

input a, b;

output sum, c_out;

assign { c_out, sum } = a + b; // Continuous assignment

endmodule

module Add_half (sum, c_out, a, b );

input a, b;

output sum, c_out;

reg sum, c_out;

always @ ( a or b)

begin

sum = a ^ b;

c_out = a & b;

end

endmodule

Structural v.s. Behavioral
• Verilog can be structural or behavioral
• Structural definition specifies the gates and their connections explicitly
• Behavioral definition specifies the functionality of a design
• Does not contain any structural information such as transistors or gates
• Logic synthesis software implements the structural
Behavioral Example2 Bit Comparator

module comparator (a_greater, b_greater, equal, a, b);

input a, b;

output a_greater, b_greater, equal;

reg a_greater, b_greater, equal;

always @(a or b) // either a or b changes

begin

if (a > b)

begin

a_greater = 1;

b_greater = 0;

equal = 0;

end

if (a<b)

begin

a_greater = 0;

b_greater = 1;

equal = 0;

end

if (a==b)

begin

a_greater = 0;

b_greater = 0;

equal = 1;

end

end

endmodule

Alternate comparator

module comparator (a_greater, b_greater, equal, a, b);

input a, b;

output a_greater, b_greater, equal;

assign a_greater = (a > b) ? 1 : 0;

assign b_greater = (a < b) ? 1 : 0;

assign equal = (a==b) ? 1 : 0;

endmodule

Uses a conditional continuous assignment to set the outputs.

Clarification
• Registers are used when an output is updated on an event. The value must be held until a new event updates that value.
• Assign statements are used when the output is continuously being assigned.
Using Verilog on Sun
• Create your Verilog module in a text file entitled:

% vi filename.v

• Compile the file using the command

% verilog filename.v

Testbench
• Manipulate the module inputs to observe the circuit reaction
• Uses module hierarchy
• Introduces the concept of delay
Sample Testbench for a Half Adder

module tbench;

reg a,b; // regs connect to module inputs

wire sum,cout; // wires connect to module outputs

initial

begin

a = 0, b = 0; //time 0

#5 a = 1, b = 0; //time 5

#3 a = 1, b = 1; //time 8

#4 a = 0, b = 1; //time 12

#52 a = 0, b = 0; //time 64

#70 \$finish; //stops the simulation

end

initial

begin

\$monitor(\$time,”a = %b, b=%b cout=%b sum=%b”,a,b,cout,sum);//displays the variable values at each

//unit of time that an event occurs

end

endmodule

Testbench Results

Compiling source file "ha.v"

Compiling source file "tbench.v"

Highest level modules:

tbench

0a = 0, b=0 cout=0 sum=0

5a = 1, b=0 cout=0 sum=1

8a = 1, b=1 cout=1 sum=0

12a = 0, b=1 cout=0 sum=1

64a = 0, b=0 cout=0 sum=0

"tbench.v": \$finish at simulation time 134

Arrays
• Arrays can be expressed in Verilog
• Can be used for inputs, outputs, wires, regs,…
• Ex: 4 bit input

input [3:0] A;

Array Example

module xor_demo(xor_group,xor_bit,A,B);

input [3:0] A, B;

output [3:0] xor_group,xor_bit;

assign xor_group = A ^ B;

assign xor_bit[0] = A[0] ^ B[0];

assign xor_bit[1] = A[1] ^ B[1];

assign xor_bit[2] = A[2] ^ B[2];

assign xor_bit[3] = A[3] ^ B[3];

endmodule

Array Test bench

module tbench;

reg [3:0] A, B;

wire [3:0] xor_group,xor_bit;

xor_demo M1(xor_group,xor_bit,A,B);

initial begin

A = 0; B = 0;

#5 A = 4'b0001; B = 4'b1100;

#10 A = 4'd5; B = 4'd10;

#5 A = 4'hF; B=4'hE;

end

initial begin

#40 \$finish;

end

initial begin

\$monitor(\$time,"A=%b B=%b group=%b bit=%b",A,B,xor_group,xor_bit);

end

endmodule

Xor Array Results

Compiling source file "xor.v"

Compiling source file "xtbench.v"

Highest level modules:

tbench

0A=0000 B=0000 group=0000 bit=0000

5A=0001 B=1100 group=1101 bit=1101

15A=0101 B=1010 group=1111 bit=1111

20A=1111 B=1110 group=0001 bit=0001

L18 "xtbench.v": \$finish at simulation time 40

Parameters
• Parameters can be used to name integers
• Parameter declaration is done when you define the port list
• Ex: parameter true = 1’b1;

parameter false = 1’b0;

parameter stop = 5’h1F;

a = 1, b = 0

a: accelerator

b: brake

low

stopped

b = 1

b = 1

b = 1

a = 1, b = 0

b = 1

medium

high

a = 1, b = 0

a = 1, b = 0

FSM Example: Car

accelerator

brake

speed

clock

Behavioral Description

module car(speed, a, b, clock);

input a, b, clock;

output [1:0] speed;

reg [1:0] speed;

parameter stopped = 2’b00;

parameter fast = 2’b11;

always @(posedge clock or b)

begin

if (b == 1 && speed != stopped)

speed = speed – 1;

else if (b == 0 && a == 1 && speed != fast)

speed = speed + 1;

end

endmodule