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In-Circuit Test Concepts Part 3 Digital In-circuit Michael J Smith [email protected] Web Seminar Series. Part 1 – In-Circuit Test Overview What and Why In-Circuit Test? The Defect Spectrum In-circuit Test System Architecture Part 2 - In-Circuit Analog Measurement

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In circuit test concepts part 3 digital in circuit michael j smith michael j smith@teradyne com

In-Circuit Test ConceptsPart 3DigitalIn-circuitMichael J [email protected]


Web seminar series
Web Seminar Series

  • Part 1 – In-Circuit Test Overview

    • What and Why In-Circuit Test?

    • The Defect Spectrum

    • In-circuit Test System Architecture

  • Part 2 - In-Circuit Analog Measurement

    • Shorts and Opens Testing

    • 2,3,4,6 Wire Measurement

    • R,C,L, Diode, Zener, Transistor Measurement

    • Powered Analog Testing

    • Analog Digital Opens Testing

  • Part 3 - In-Circuit Digital Testing

    • Digital Vectors

    • Backdriving

    • Inhibits and Disables

    • Bus Testing

    • Boundary Scan

    • ISP and FLASH programming

  • Part 4 - In-Circuit Program Development Process


Agenda in circuit digital testing
Agenda - In-Circuit Digital Testing

  • Introduction

  • Test Flow

  • Backdriving

  • Digital Vectors

  • Inhibits and Disables

  • BusTests

  • Boundary Scan / NAND Tree

  • Value Added Functions


What is in circuit test
What is In-Circuit Test?

  • Uses a “Bed of Nails” to access as many electrical nodes on the Unit Under Test (UUT) as possible.

  • Voltage and current source(s) and measure(s) are used to test analog devices, one device at as time, using guarding techniques to negate the effects of other devices.

  • A technique called backdriving, using voltage overdriving, is used to test digital devices in isolation with digital vectors by voltage forcing techniques.


Defect spectrum
Defect Spectrum

ICT finds defects!

But it does not normally find potential defects

in solder quality!


Program flow analog tests
Program Flow - Analog Tests

  • Capacitor Discharge

  • Contact Test

  • Shorts Test

  • Analog Test – Un-Powered

    • Resistor

    • Capacitor

    • Inductor

    • Diode

    • Transistors

  • Analog Digital Opens

  • Power Board

  • Power Up Tests

    • Op-Amps.

  • Un-Power Board


Program flow digital tests
Program Flow – Digital Tests

  • Non Bussed Digital Tests

  • Bus Tests

  • Bussed Devices

  • Boundary Scan

    • All defects removed

  • Value Added Functions

    • ISP/FLASH programming

  • Un-Power Board


  • Backdriving node forcing
    Backdriving – Node Forcing

    • U1 is backdriven (voltage forced) to high and low

    • Current flows into U2, but most into U1

    DUT

    U2

    U1

    Test System

    DS


    Voltage level technologies

    JEDEC 8-14 Wide

    0.8 Volt Logic

    Hi Limit

    Lo Limit

    LV Logic

    240mV window

    Voltage Level Technologies

    Dual-level thresholds allow precise verification of pin logic

    The 1980-90’s

    Logic Family

    5.0

    4.5

    4.0

    3.5

    3.0

    2.5

    2.0

    1.5

    1.0

    0.5

    0

    Conventional

    Logic (TTL)

    2600mV window

    Input Voltage (V) at Device

    800mV window

    Logic “1”

    Logic “0”


    Safe backdriving

    U1

    Safe Backdriving.

    • Measure current in real time.

    • Limit current and time in production.

    • Ultra-accurate driver levels.

    • Paired driver and sensor

      • Sensors verifies the drive level with dual threshold.

    • A “stable” test.

    • Is backdriving safe?

      • Def Standard 0053 Issue 2/3

      • Investigation of Device Damage Due to Electrical Testing (WPI)

      • The Challenges of Testing Low Voltage technologies at In-Circuit Test”, Teradyne, Inc

    U2

    DS


    High performance digital pins driver

    Drive

    High

    Low

    Off

    Hold

    External

    High-Performance Digital Pins - Driver

    NOTE: Digital pins are normally hybrid (i.e., they have analog scans connected)

    15mA - 500mA

    of drive current


    High performance digital pins sensor

    Sense

    Low

    High

    “X” State

    Collect CRC

    Pull-up

    Pull-Down

    High-Performance Digital Pins - Sensor


    Other features needed for digital testing
    Other Features Needed for Digital Testing

    • Memory behind the driver sensor

      • 8K to Gigabytes

      • Din, Dout, Drive, Sense, Pass/Fail

    • Dedicated Controller

      • 1000 Test Steps

    100K -> 10Megs

    PC Controller >104ms

    High Speed Controller > 0.2ms


    A complete system
    A Complete System

    Normal Driver/Sensors and additional Clocks and Triggers.


    Truth table digital testing

    U1_B1: BURST; IC(17,18) OS(38) IH(17) IL(18) OH(38); IH(18) OL(38); IL(17) OH(38); IL(18); ID(17,18) OI(38);END BURST;

    Truth Table - Digital Testing


    Normally circuits are more than one device

    Truth Table

    Gray Code

    74LS08

    Truth Table 74LS138

    Normally Circuits Are More Than One Device

    Truth Table

    • Truth tables can be applied to each device, as if they were in isolation

      • or can they?

    74LS04




    Multi level digital isolation
    Multi-Level Digital Isolation

    Device Under Test (DUT)

    U1

    U7

    U5

    U6

    U4

    U2

    U3

    Node Used

    For

    Third-Level

    Isolation

    Node Used

    For

    Second-Level

    Isolation

    Nodes Used

    For

    DUT Test

    Nodes Used

    For

    First-Level

    Isolation


    Disables are better inhibits

    DS

    Disables Are Better Inhibits

    Net N3 is now disabled

    Net N3

    U1

    U2

    U3

    U4

    DS

    DS

    Current measurement will indicate that the net

    is not tri-state.


    Bused devices need to be tri stated
    Bused Devices Need To Be Tri-Stated

    D0

    D1

    D2

    D3

    D4

    D5

    D6

    D7

    U12

    U13

    U14

    Disable

    Disable

    Disable

    Each device is disabled and resistors are used to pull the

    bus up and down.

    Pull up and Pull down


    Multi level digital isolation software
    Multi-Level Digital Isolation Software

    • Test generator automatically isolates devices to the edge of the board

    • Backdriving is eliminated wherever possible by disables

    • Prevents outputs from changing while being backdriven

    • Prevents voltage spikes that could cause CMOS latch-up failures

    • Results in repeatable and safe digital tests

    U10

    U2

    Disable Device

    Disable Device

    U56

    Disable Device

    U12

    Edge Connector

    U1

    Inhibit

    Device Under Test


    Cycle based tests bus devices

    Truth Table

    Cycle Based Tests – Bus Devices

    • READ Cycles

    • WRITE Cycles

    TRDY

    IRDY

    D0

    D1

    D2

    D3

    D4

    D5

    D6

    D7

    AD0

    AD1

    AD2

    AD3

    AD4

    AD5

    AD6

    AD7

    U2

    C/BE

    CLK


    Other vector base tests boundary scan

    No access required

    Other Vector Base Tests - Boundary Scan

    • Remove access between pure boundary scan devices.

    U1

    U2

    TDO

    TDI

    TAP

    TAP

    TCK

    TMS

    TCK

    TDI


    Boundary scan interaction tests
    Boundary Scan Interaction Tests

    100110

    011001

    100101

    010110

    101010

    A

    1

    1

    1

    1

    1

    1

    1

    1

    1

    1

    A - Expected 111111 Actual 101010

    Find Continuity and Shorts

    Between boundary scan and normal nets


    Boundary scan virtual pin

    Test Electronics

    INSIDE

    Each Pin of the IC

    Test Electronics

    INSIDE

    Each Pin of the IC

    TDO

    TDO

    TDI

    TDI

    TMS

    TMS

    TAP

    TAP

    TCK

    TCK

    Boundary Scan Virtual Pin

    DS


    Other vector based techniques

    NAND Tree

    Other Vector-Based Techniques

    DS

    DS

    DS

    DS

    DS

    Also - XOR Tree


    Value added functions
    Value Added Functions

    • Accurate Driver Sensors

    • Memory behind the pin

    • Verification


    Value added functions isp and flash programming
    Value Added Functions ISP and FLASH Programming

    • PROM programming

      • ADDRESS(00000000) DATA(AF);

      • ADDRESS (00000001) DATA(55);

      • ADDRESS (00000010) DATA(E1);

      • ADDRESS (00000011) DATA(75);

  • Serial PROMs and ISP devices

    • Serial data streams

  • WE

    RD

    D0

    D1

    D2

    D3

    D4

    D5

    D6

    D7

    AD0

    AD1

    AD2

    AD3

    AD4

    AD5

    AD6

    AD7

    PROM

    CE

    DO

    CLK

    DI

    Serial

    PROM

    PROG

    RST


    Webinar sequels
    Webinar Sequels

    • Part 1 – In-Circuit Test Overview

      • http://www.teradyne.com/atd/resource/type/web_recordings.html

    • Part 2 – In-Circuit Test – Analog In-circuit

      • http://www.teradyne.com/atd/resource/type/web_recordings.html

    • Part 4 - In-Circuit Program Development Process

      • Cad Translation

      • Libraries

        • Analog

        • Digital

      • Automatic Test Generation Process

      • Debug/Auto Debug

      • Program Release


    In circuit test concepts part 3 digital in circuit michael j smith michael j smith@teradyne com1

    In-Circuit Test ConceptsPart 3DigitalIn-circuitMichael J [email protected]


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