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中科院研究生院课程: VLSI 测试与可 测试 性设计 PowerPoint Presentation
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中科院研究生院课程: VLSI 测试与可 测试 性设计

中科院研究生院课程: VLSI 测试与可 测试 性设计

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中科院研究生院课程: VLSI 测试与可 测试 性设计

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  1. 中科院研究生院课程:VLSI测试与可测试性设计 第4讲 逻辑与故障模拟 李晓维 中科院计算技术研究所 Email: lxw@ict.ac.cn http://test.ict.ac.cn

  2. Chapter 3 Logic and Fault Simulation

  3. About the Chapter • Circuit simulation models • Logic simulation techniques • Fault simulation techniques

  4. Logic and Fault Simulation • Introduction • Simulation models • Logic simulation • Fault simulation • Concluding remarks

  5. Specification Manual design or via Synthesis Testbench Development Circuit Description Input Stimuli Expected Responses yes Simulated Responses Bug? Response Analysis no Next Design Stage Logic Simulation • Predict the behavior of a design prior to its physical realization • Design verification

  6. Fault Simulation • Predicts the behavior of faulty circuits • As a consequence of inevitable fabrication process imperfections • An important tool for test and diagnosis • Estimate fault coverage • Fault simulator • Test compaction • Fault diagnosis

  7. Logic and Fault Simulation • Introduction • Simulation models • Logic simulation • Fault simulation • Concluding remarks

  8. A H K L B J C E F G3 G1 G4 G2 Gate-Level Network • The interconnections of logic gates

  9. Combinational Logic x1 z1 x2 z2 xn zm y1 Y1 y2 Y2 yl Yl Flip-Flops clock Sequential Circuits • The outputs depend on both the current and past input values xi: primary input (PI) zi: primary output (PO) yi: pseudo primary input (PPI) Yi: pseudo primary output (PPO)

  10. PresetB PresetB DFF Q D Q Clock QB Clock QB ClearB D ClearB A Positive Edge-Triggered D-FF

  11. HA; c c inputs: a, b; a a outputs: c, f; e e AND: A1, (a, b), (c); d d f f AND: A2, (d, e), (f); b b OR: O1, (a, b), (d); HA HA NOT: N1, (c), (e); FA; D D inputs: A, B, C; A A Carry Carry HA1 HA1 outputs: Carry, Sum; F F E E B B HA2 HA2 HA: HA1, (A, B), (D, E); Sum Sum C C HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); Example: A Full-Adder

  12. Logic Symbols • The most commonly used are 0, 1, u and Z • 1 and 0 • true and false of the two-value Boolean algebra • u • Unknown logic state (maybe 1 or 0) • Z • High-impedance state • Not connected to Vdd or ground

  13. Ternary Logic • Three logic symbols: 0, 1, and u

  14. 1 A u u K u B u C u 0 1 A 0 or 1 0 K G3 G3 0 or 1 G1 G1 G4 G4 B 1 or 0 C 0 or 1 G2 G2 0 Information Loss of Ternary Logic • Simulation based on ternary logic is pessimistic • A signal may be reported as unknown when its value can be uniquely determined as 0 or 1

  15. e1 o1 x1 pull-up or down G3 G1 G2 e2 o2 y x2 DFF Resolution Function e3 o3 x3 High-Impedance State Z • Tri-state gates permit several gates to time-share a common wire, called bus • A signal is in high-impedance state if it is connected to neither Vdd nor ground

  16. Logic Element Evaluation Methods • Choice of evaluation technique depends on • Considered logic symbols • Types and models of logic elements • Commonly used approaches • Truth table based • Input scanning • Input counting • Parallel gate evaluation

  17. Truth Table Based Gate Evaluation • The most straightforward and easy to implement • For binary logic, 2n entries for n-input logic element • May use the input value as table index • Table size increases exponentially with the number of inputs • Could be inefficient for multi-valued logic • A k-symbol logic system requires a table of 2mn entries for an n-input logic element • m = log2k • Table indexed by mn-bit words

  18. A H K B E J C G3 G1 G4 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 0 1 0 1 0 0 0 0 G2 Parallel Gate Evaluation • Exploit the inherent concurrency in the host computer • A 32-bit computer can perform 32 logic operations in parallel

  19. Timing Models • Transport delay • Inertial delay • Wire delay • Function element delay model

  20. A F B=1 A (a) Nominal delay dN = 2 ns F (b) Rise/fall delay dr = 2 ns df = 1.5 ns A F 1 1 2 1.5 1.5 1 2 2 1 2 A (c) Min-max delay dmin = 1 ns dmax = 2 ns F G 2 Transport Delay • The time duration it takes for the effect of gate input changes to appear at gate outputs

  21. A F dI = 1.5 ns, dN = 3 ns B=1 (a) Pulse duration less than dI A F (b) Pulse duration longer than dI 2 1 3 2 3 A F G Inertial Delay • The minimum input pulse duration necessary for the output to switch states

  22. p q b da-b a c da-c d da-d Wire Delay • Wires are inherently resistive and capacitive • It takes finite time for a signal to propagate along a wire

  23. Functional Element Delay Model • For more complicated functional elements like flip-flops

  24. Modeling Levels

  25. Logic and Fault Simulation • Introduction • Simulation models • Logic simulation • Fault simulation • Concluding remarks

  26. start no next vector? end yes read in next input vector v run compiled code with input v in host machine output simulation results Compiled Code Simulation • Translate the logic network into a series of machine instructions that model the gate functions and interconnections

  27. before optimization after optimization 1 (a) A A B B (b) A A A A (c) 0 A 1 (d) A (e) A Logic Optimization • Enhance the simulation efficiency

  28. 0  1 A H: 0  1 K: 1  0 0  1 B G3 G1 G4 C E: 1 J: 0 1 G2 Event-Driven Simulation • Event: the switching of a signal’s value • An event-driven simulator monitors the occurrences of events to determine which gates to evaluate

  29. start read in initial condition no yes Q empty? no evaluate next gate g from Q next vector? end yes no output change? read in new input vector yes put g’s fanout gates in Q put active Pis’ fanout gates in Q Zero-Delay Event-Driven Simulation • Gates with events at their inputs are places in the event queue Q

  30. t0 p, vp+ q, vq+ r, vr+ s, vs+ t1 w, vw+ ti Nominal-Delay Event-Driven Simulation • Need a smarter scheduler than the event queue • Not only which gates but also when to evaluate

  31. start yes no yes end Next time stamp? LE empty? LA empty? yes no no get next time stamp t get next gate g from LA get next event (g, vg+) from LE retrieve current event list LE yes evaluate g and schedule (g, vg+) at t+delay(g) vg+==vg? no vgvg+ append g’s fanout gates to activity list LA Two-Pass Event-Driven Simulation

  32. Event-Driven Algorithm (Example)

  33. A H K B E J C G3 G1 G4 G2 Example

  34. Compiled-Code vs. Event-Driven Simulation • Compiled-code • Cycle-based simulation • High switching activity circuits • Parallel simulation • Limited by compilation times • Event-driven • Implementing gate delays and detecting hazards • Low switching activity circuits • More complicated memory management

  35. Logic and Fault Simulation • Introduction • Simulation models • Logic simulation • Fault simulation • Concluding remarks

  36. Fault Simulation • Introduction • Serial Fault Simulation • Parallel Fault Simulation • Deductive Fault Simulation • Concurrent Fault Simulation • Differential Fault Simulation • Fault Detection • Comparison of Fault Simulation Techniques • Alternative to Fault Simulation • Conclusion

  37. Introduction • What is fault simulation? • Given • A circuit • A set of test patterns • A fault model • Determine • Faulty outputs • Undetected faults • Fault coverage

  38. Time Complexity • Proportional to • n: Circuit size, number of logic gates • p: Number of test patterns • f: Number of modeled faults • Since f is roughly proportional to n, the overall time complexity is O(pn2)

  39. Serial Fault Simulation • First, perform fault-free logic simulation on the original circuit • Good (fault-free) response • For each fault, perform fault injection and logic simulation • Faulty circuit response

  40. Test vectors Fault - free circuit Comparator f1 detected? Circuit with fault f1 Comparator f2 detected? Circuit with fault f2 Comparator fn detected? Circuit with fault fn Serial Fault Simulation

  41. start F collapsed fault list fault-free simulation for all patterns no end next fault? yes get next fault f from F reset pattern counter no next pattern? yes get next pattern p fault simulation for p no yes mis-match? delete f from F Algorithm Flow

  42. A H f: A stuck-at 1 K L g: J stuck-at 0 B C E F J G3 G1 G4 G2 Example

  43. Fault Dropping • Halting simulation of the detected fault • Example • Suppose we are to simulate P1, P2, P3 in order • Fault f is detected by P1 • Do not simulate f for P2, P3 • For fault grading • Most faults are detected after relatively few test patterns have been applied • For fault diagnosis • Avoided to obtain the entire fault simulation results

  44. Pro and Con • Advantages • Easy to implement • Ability to handle a wide range of fault models (stuck-at, delay, Br, …) • Disadvantages • Very slow

  45. Parallel Fault Simulation • Exploit the inherent parallelism of bitwise operations • Parallel fault simulation [Seshu 1965] • Parallel in faults • Parallel pattern fault simulation [Waicukauski 1986] • Parallel in patterns

  46. Parallel Fault Simulation • Assumption • Use binary logic: one bit is enough to store logic signal • Use w-bit wide data word • Parallel simulation • w-1 bit for faulty circuits • 1 bit for fault-free circuit • Process faulty and fault-free circuit in parallel using bitwise logic operations

  47. Bit 0: fault - free circuit Bit 1: circuit with s - a - 0 c Bit 2: circuit with s - a - 1 f 1 1 1 s - a - 0 detected c a 1 0 1 1 0 1 1 1 1 e b 1 0 1 c s - a - 0 g 0 0 0 d s - a - 1 f 0 0 1 Parallel Fault Simulation

  48. A H f: A stuck-at 1 K L g: J stuck-at 0 B C E F J Gf A H 0 0 1 1 0 0 K L G3 G3 G1 G1 G4 G4 B J C E F G2 G2 Gg Fault Injection

  49. Example

  50. Pro and Con • Advantages • A large number of faults are detected by each pattern when simulating the beginning of test sequence • Disadvantages • Only applicable to the unit or zero delay models • Faults cannot be dropped unless all (w-1) faults are detected