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Hardware/Software Codesign with SystemC

Hardware/Software Codesign with SystemC. HM-ES-th1 Les 7. Van Algoritme naar RTL. Als voorbeeld bekijken we een Single-Purpose Processor die de Greatest Common Divider uitrekent . We beginnen met een functional level SystemC model waarin het algoritme wordt beschreven. gcd. y_i.

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Hardware/Software Codesign with SystemC

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  1. Hardware/Software Codesign with SystemC HM-ES-th1 Les 7

  2. Van Algoritmenaar RTL • Alsvoorbeeldbekijken we een Single-Purpose Processor die de Greatest Common Divider uitrekent. • We beginnen met een functional level SystemC model waarin het algoritmewordtbeschreven. gcd y_i x_i r_o

  3. SystemC Untimed Model template <typenameT> SC_MODULE(gcd) { sc_in<T> x_i, y_i; sc_out<T> r_o; SC_CTOR(gcd) { SC_METHOD(run); sensitive << x_i << y_i; } private: void run() { T x = x_i.read(); T y = y_i.read(); while (x != y) { if (x > y) { x -= y; } else { y -= x; } } r_o.write(x); } }; Euclid'salgorithm300 BC

  4. SystemC Test Bench template <typenameT> SC_MODULE(tb_gcd) { sc_in<T> r_i; sc_out<T> x_o, y_o; SC_CTOR(tb_gcd) { SC_THREAD(run); } private: void check(constT& x, constT& y, constT& r) { wait(10, SC_NS); x_o.write(x); y_o.write(y); wait(10, SC_NS); assert(r_i.read() == r); } void run() { check(0, 0, 0); check(234, 96, 6); check(12345, 67891, 1); check(12345, 67890, 15); check(12345, 12345, 12345); wait(10, SC_NS); x_o.write(0); y_o.write(0); sc_stop(); // ... tb_gcd x_o y_o gcd y_i x_i r_0 r_i

  5. SystemC sc_main intsc_main(intargc, char *argv[]) { gcd<unsignedint> gcd("gcd"); tb_gcd<unsignedint> tb_gcd("tb_gcd"); sc_buffer<unsignedint> x, y, r; gcd.x_i(x); gcd.y_i(y); gcd.r_o(r); tb_gcd.x_o(x); tb_gcd.y_o(y); tb_gcd.r_i(r); sc_start(); return 0; } • Nu kunnen we timing informatieaan het model toevoegen om tekijken of ditalgoritmeaan de timing eisenvoldoet.

  6. SystemC approximately-timed template <typenameT> SC_MODULE(gcd) { // idem void run() { while(1) { wait(); T x = x_i.read(); T y = y_i.read(); wait(10, SC_NS); while (x != y) { if (x > y) { x -= y; } else { y -= x; } wait(10, SC_NS); } r_o.write(x); } } }; Voegwait(…, SC_NS)statements toe!

  7. SystemC approximately-timed template <typenameT> SC_MODULE(tb_gcd) { // idem void check(constT& x, constT& y, constT& r) { autostart_time_stamp = sc_time_stamp(); x_o.write(x); y_o.write(y); wait(); wait(10, SC_NS); assert(r_i.read() == r); autoend_time_stamp = sc_time_stamp(); cout << "@: " << sc_time_stamp() << ": gcd(" << x << "," << y << ") = " << r << " duration: " << end_time_stamp - start_time_stamp << endl; }

  8. SystemC cycle accurate • Steldatditvoldoetaan de timing specificaties. • We maken nu eennauwkeuriger model door het clock signaalclk toe tevoegen. • We voegenmeteeneengo_i en done_ohandshakesignaal toe. Waarom? gcd y_i go_i x_i clk done_o r_o

  9. SystemC cycle accurate template <typenameT> SC_MODULE(gcd) { sc_in_clkclk; sc_in<bool> go_i; sc_in<T> x_i, y_i; sc_out<bool> done_o; sc_out<T> r_o; SC_CTOR(gcd) { SC_THREAD(run); sensitive << clk.pos(); x_i gcd y_i go_i x_i y_i clk go_i done_o r_o done_o r_o

  10. SystemC cycle accurate voidrun() { wait(); while(1) { do { wait(); } while (!go_i.read()); T x = x_i.read(); T y = y_i.read(); wait(); while (go_i.read() && x != y) { if (x > y) { x -= y; } else { y -= x; } wait(); } if (go_i.read()) { r_o.write(x); done_o.write(true); } do{ wait(); } while (go_i.read()); done_o.write(false); } }

  11. SystemC cycle accurate template <typenameT> SC_MODULE(tb_gcd) { sc_in<bool> done_i; sc_in<T> r_i; sc_out<bool> go_o; sc_out<T> x_o, y_o; SC_CTOR(tb_gcd) { SC_THREAD(run); sensitive << done_i; } private: void check(constT& x, constT& y, constT& r) { autostart_time_stamp = sc_time_stamp(); x_o.write(x); y_o.write(y); go_o.write(true); wait(); assert(r_i.read() == r); autoend_time_stamp = sc_time_stamp(); cout << "@: " << sc_time_stamp() << ": gcd(" << x << "," << y << ") = " << r << " duration: " << end_time_stamp - start_time_stamp << endl; go_o.write(false); wait();

  12. SystemC RTL • Ga ervan uit dat de benodigde RTL componenten beschikbaar zijn (zie hand-outs). • Ontwerp en implementeer Datapath en Controller.

  13. Combinational components

  14. Sequential components

  15. … external control inputs external data inputs controller datapath … … registers datapath control inputs next-state and control logic controller datapath datapath control outputs functional units state register … … external control outputs external data outputs … … a view inside the controller and datapath controller and datapath single-purpose processor basic model

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