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Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems

Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems

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Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems

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  1. Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems Part 2: designing in Esterel v7 Gérard Berry Chief Scientist www.esterel-technologies.com Gerard.Berry@esterel-technologies.com G. Berry, VLSI'2004 synchronous tutorial, 2 -

  2. Agenda - Part 2Designing in Esterel v7 • The Esterel principle: Write Things Once • Pure signals and basic control • General signals and datapath equations • Program units • Esterel v7 examples • Comparison with HDLs G. Berry, VLSI'2004 synchronous tutorial, 2 -

  3. Agenda - Part 2The Esterel Language • The Esterel principle: Write Things Once • Pure signals and basic control • General signals and datapath equations • Program units • Esterel v7 examples • Comparison with HDLs G. Berry, VLSI'2004 synchronous tutorial, 2 -

  4. Imperative specification Emit O as soon has A and B have arrived. Reset behavior each R R? R? A? B? R? R? A? B? O! B? O! A? O! G. Berry, VLSI'2004 synchronous tutorial, 2 -

  5. Imperative specification multiple copies => explosion R? R? A? B? R? R? A? B? O! B? O! A? O! G. Berry, VLSI'2004 synchronous tutorial, 2 -

  6. The key idea: Write Things Once loop [ await A || await B ] ; emit O each R • concurrency • sequencing • preemption • full orthogonality G. Berry, VLSI'2004 synchronous tutorial, 2 -

  7. A? B? [ await A || await B ] A? B? B? A? [ await A || await B ] ; emit O A? B? A? B? O! B? O! A? O! R? loop [ await A || await B ] ; emit O each R R? A? B? R? R? A? B? O! B? O! A? O! G. Berry, VLSI'2004 synchronous tutorial, 2 -

  8. The key idea: Write Things Once loop [ await A || await B ] ; emit O each R • concurrency • sequencing • preemption • full orthogonality G. Berry, VLSI'2004 synchronous tutorial, 2 -

  9. N-way Concurrency loop [ await A || await B || await C ] ; emit O each R scales linearly vs. exponential automata blowup G. Berry, VLSI'2004 synchronous tutorial, 2 -

  10. SyncCharts (C. André)Synchronous Hierarchical Automata Esterel synchronous semantics G. Berry, VLSI'2004 synchronous tutorial, 2 -

  11. Agenda - Part 2The Esterel Language • The Esterel principle: Write Things Once • Pure signals and basic control • General signals and datapath equations • Program units • Esterel v7 examples • Comparison with HDLs G. Berry, VLSI'2004 synchronous tutorial, 2 -

  12. Standard (Mealy) pure signals input I; output O; signal S in ... end • Emitted and received in the same cycle (broadcast) • signal present if and only if emitted (default absent) • pre(S) operator yields status at previous cycle • => sequential expressions • Multiple drivers allowed emit S; if I and not pre(I) then ... // rising edge G. Berry, VLSI'2004 synchronous tutorial, 2 -

  13. Signal emission emitS sustain S Basic control and expressions • Sequential control flow • pause • await S • every S do p end • Combinational control flow • sequence: “;” • concurrency: “||” • abort p when S • if S then p else q end • loop p end • Sequential expressions • if pre(S) • await S and not pre(S) G. Berry, VLSI'2004 synchronous tutorial, 2 -

  14. Sequencing emit A ; emit B ; pause ; emit C G. Berry, VLSI'2004 synchronous tutorial, 2 -

  15. Sequencing emit A ; emit B ; pause ; emit C A G. Berry, VLSI'2004 synchronous tutorial, 2 -

  16. Sequencing emit A ; emit B ; pause ; emit C A B G. Berry, VLSI'2004 synchronous tutorial, 2 -

  17. Sequencing wait for a cycle emit A ; emit B ; pause ; emit C A B G. Berry, VLSI'2004 synchronous tutorial, 2 -

  18. Sequencing emit A ; emit B ; pause ; emit C C A B G. Berry, VLSI'2004 synchronous tutorial, 2 -

  19. Looping loop emit A ; emit B ; pause ; emit C end loop C A B G. Berry, VLSI'2004 synchronous tutorial, 2 -

  20. Looping loop emit A ; emit B ; pause ; emit C end loop C A B G. Berry, VLSI'2004 synchronous tutorial, 2 -

  21. Looping loop emit A ; emit B ; pause ; emit C end loop C A B G. Berry, VLSI'2004 synchronous tutorial, 2 -

  22. Looping loop emit A ; emit B ; pause ; emit C end loop C A A B G. Berry, VLSI'2004 synchronous tutorial, 2 -

  23. Looping loop emit A ; emit B ; pause ; emit C end loop • Loop back in the same cycle • Non-instantaneous body • Loop invariant: cannot reenter if the body still executes C A B A B G. Berry, VLSI'2004 synchronous tutorial, 2 -

  24. Decision emit A ; emit B ; pause ; loop if C then emit D else emit Q end if; if pre(E) then emit F end if; pause end loop C C E E D D Q A F F B G. Berry, VLSI'2004 synchronous tutorial, 2 -

  25. Concurrency { await A ; emit C || await B ; emit D } ; emit E A B D E C • Start parallel statements in the same cycle • Terminate parallel block once all branches terminated B A C E D A B C D E G. Berry, VLSI'2004 synchronous tutorial, 2 -

  26. Preemption abort pause ; pause ; emit A when B ; emit C • Normal termination • Aborted termination • Aborted termination; emit A preempted A C B C B C G. Berry, VLSI'2004 synchronous tutorial, 2 -

  27. When to react? await A ; emit B await immediate A ; emit B A A A B B A A A B B • Non-immediate (default) form does not react to signals arrived during the initial instance (before the first tick) G. Berry, VLSI'2004 synchronous tutorial, 2 -

  28. When to kill? abort pause; emit A ; pause; emit B when C; emit D weak abort pause; emit A ; pause; emit B when C; emit D C C A D D C C B D A D A • Strong abort (default) kills all emissions during the abort cycle • Weak abort gives signal emissions the last will G. Berry, VLSI'2004 synchronous tutorial, 2 -

  29. Four (react, kill) possibilities when to react toS weak abortpwhenS abortpwhenS next abortp when immediateS weak abortp when immediateS now when to killP next now G. Berry, VLSI'2004 synchronous tutorial, 2 -

  30. The Esterel Runner abort loop abort run Slowly when 100 Meter; abort every Step do run Jump|| run Breathe end every when 15 Second; runFullSpeed each Lap when 2 Lap G. Berry, VLSI'2004 synchronous tutorial, 2 -

  31. defines exit point exitHeartAttack trap HeartAttack in every Morning do abort loop abort run Slowly when 100 Meter; abort every Step do run Jump|| run Breathe||<CheckHeart> end every when 15 Second; run FullSpeed each Lap when 2 Lap end every handle HeartAttack do runRushToHospital end trap G. Berry, VLSI'2004 synchronous tutorial, 2 -

  32. Programs mean what they say module SPEED : % computes exact speed input Centimeter, Second; output Speed : integer; loop var Distance:= 0 : integer in abort every Centimeter do Distance := Distance + 1 end every when Second; emit Speed(Distance) end var end loop end module G. Berry, VLSI'2004 synchronous tutorial, 2 -

  33. module REGUL: function Regfun (integer, integer) : integer; input Centimeter, Second; input value GasPedal: integer; output Regul: integer; signal Speed: integer in run SPEED || await Speed; sustain Regul(Regfun(?Speed, ?GasPedal)) end signal end module G. Berry, VLSI'2004 synchronous tutorial, 2 -

  34. abort sustain DmaReq when DmaOk; abort abort every ByteIn do emit ByteOut (?ByteIn) end every when DmaEnd when 10 times MilliSecond do emit TimeOut end abort G. Berry, VLSI'2004 synchronous tutorial, 2 -

  35. abort sustain DmaReq when DmaOk; abort trap ParityError in abort every ByteIn do emit ByteOut (?ByteIn) end every || every 4 ByteIn do if BadParity (?ByteIn) then exit ParityError end end every when DmaEnd handle ParityError do ...... end trap when 10 MilliSecond do emit TimeOut end abort G. Berry, VLSI'2004 synchronous tutorial, 2 -

  36. Signals to communicate with the environment or within the program Expressions are sequential because of pre Control is explicit and sequential Waiting and preemption statements give behavior desctiption power Programming Concepts Summary no need to separate combinational and sequential part G. Berry, VLSI'2004 synchronous tutorial, 2 -

  37. Agenda - Part 2The Esterel Language • The Esterel principle: Write Things Once • Pure signals and basic control • General signals and datapath equations • Program units • Esterel v7 examples • Comparison with HDLs G. Berry, VLSI'2004 synchronous tutorial, 2 -

  38. Extensions in Esterel v7 language Goal: remove the current limitations of Esterel v5 much more expressive, but very same semantics • Mix of Esterel imperative and Lustre equational styles • Better modularity, (mild) object orientation • data, interface, and module units • data and interface inheritance • Structured ports, arrays, more signal kinds • value, temp, registered, etc. • Static code replication (for ... dopar) • Support for Moore machines • Numerical encodings • binary, onehot, Gray, etc. • 100% synthesizable to RTL/C/System-C, modular optimization G. Berry, VLSI'2004 synchronous tutorial, 2 -

  39. Signal arrays input I [10]; output O [N] signal S [256] in ... end • Composed of independent individual components • S[i] yields status at current cycle for component i • pre(S[i]) yields status at previous cycle emit S[i]; if S[i] then ... if pre(S[i]) then ... emit O <= I and S// pointwise extension G. Berry, VLSI'2004 synchronous tutorial, 2 -

  40. Registered (Moore) pure signals output O : reg; signal S [10] : reg1 in ... end • Emitted at one cycle and and received in the next cycle • S yields status at current cycle, • next(S) yields status at next cycle • => sequential expressions • Initial status 0 for reg, 1 for reg1 emit next S; if S then ... if next(S[3]) then ... G. Berry, VLSI'2004 synchronous tutorial, 2 -

  41. Valued signals input I : integer; output O : integer; signal S [10]: integer in ... end • status reactive (not persistent), as for pure signal • value is persistent, ?S returns the value • value changes only when status present (enable) • no multiple emitters by default emit ?S <= 2 if S then emit O(?S+1) G. Berry, VLSI'2004 synchronous tutorial, 2 -

  42. Combined valued signals output O [10] : integer combine +; signal S : integer combine * in ... end • mutiple emitters allowed • combination function combines emitted values { signal S ; integer combine + in emit ?S <= 2 || emit ?S <= 3; end signal || emit ?O[1](?S+1) } // ?O[1] = (2+3)+1 = 6 G. Berry, VLSI'2004 synchronous tutorial, 2 -

  43. Advanced Signals output O : reg integer; // Moore valued output O : reg integer combine +; // combined Moore valued output O [10] : value integer; // value-only, persistent output O : temp integer; // temporary, non-persistent Allow fine-grain control over hardware implementation in particular register allocation G. Berry, VLSI'2004 synchronous tutorial, 2 -

  44. Data-path equations emit { A[1], B <= I or I if (?I > 0) ?X <= 2 if B next ?Y[2] <= pre(?X) + 1 if B and not pre(B) } • equations are concurrent and unordered • dependencies must be combinationally acyclic • semantics = solution (no delta-cycles, etc) G. Berry, VLSI'2004 synchronous tutorial, 2 -

  45. Agenda - Part 2The Esterel Language • The Esterel principle: Write Things Once • Pure signals and basic control • General signals and datapath equations • Program units • Esterel v7 examples • Comparison with HDLs G. Berry, VLSI'2004 synchronous tutorial, 2 -

  46. Data units • data units defined host data objects and parameters • data units are generic and extensible data D1 : constant N : integer = 4; type Time; // host (defined in host language constant Noon : Time; // host end data data D2 : extends D1; // inherits all objects from D1 function Next (Time) : Time; // host end data G. Berry, VLSI'2004 synchronous tutorial, 2 -

  47. Interfaces • Group logically related signals • Can be extended and mirrored interface Intf1 : input I, J; end interface interface Intf2 : extends Intf1; // imports I, J output O; end interface module M : extends mirror Intf2;// input O, output I,J G. Berry, VLSI'2004 synchronous tutorial, 2 -

  48. Ports • A port is a group of signals typed by an interface • Component accessed through dot notation module M : port P : Intf2; if pre(P.O) then emit P.I end end module G. Berry, VLSI'2004 synchronous tutorial, 2 -

  49. data binding signal binding Modules • A module has an interface and an executable behavior • It can extend interfaces and data units and declare • local objects • It can be instantiated in another module module M : extends data D; extends interface Intf1; extends mirror interface Intf2; port P : Intf3; every P.Reset do ... end every ... run SubMod[constant 4 / N, X / I, Y / O] end module G. Berry, VLSI'2004 synchronous tutorial, 2 -

  50. Agenda - Part 2The Esterel Language • The Esterel principle: Write Things Once • Pure signals and basic control • General signals and datapath equations • Program units • Esterel v7 examples • Comparison with HDLs G. Berry, VLSI'2004 synchronous tutorial, 2 -