1 / 22

Tecnologia CMOS I passi principali per la realizzazione di transistori a canale n e a canale p

Tecnologia CMOS I passi principali per la realizzazione di transistori a canale n e a canale p. input. GND. VDD. output. n+. n+. n+. p+. p+. p+. n-well. n-well. p substrate. p substrate. input. GND. VDD. output. n+. n+. n+. p+. p+. p+. n-well. p substrate. +SiO 2.

timothy-hayden
Download Presentation

Tecnologia CMOS I passi principali per la realizzazione di transistori a canale n e a canale p

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Tecnologia CMOS I passi principali per la realizzazione di transistori a canale n e a canale p

  2. input GND VDD output n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  3. input GND VDD output n+ n+ n+ p+ p+ p+ n-well p substrate +SiO2 +SiO2

  4. n-well n-well mask p substrate photoresist SiO2 n+ n+ n+ p+ p+ p+ n-well p substrate p substrate

  5. n-well p substrate photoresist SiO2 n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  6. active mask n-well p substrate photoresist Nitride n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  7. channel stop mask n-well p substrate n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  8. n-well n-well mask p substrate n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  9. n-well p substrate n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  10. n-well p substrate n+ n+ n+ p+ p+ p+ n-well n-well gate oxide p substrate p substrate

  11. polysilicon mask n-well p substrate polysilicon n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  12. n+ mask n-well p substrate n+ n+ n+ n+ n+ n+ p+ p+ p+ n-well n-well gates p substrate p substrate n-well p substrate

  13. p+ mask n-well p substrate n+ n+ n+ n+ n+ n+ p+ p+ p+ p+ p+ p+ n-well n-well p substrate p substrate n-well p substrate

  14. n-well n+ n+ n+ p+ p+ p+ p substrate n-well p substrate

  15. contact mask n+ n+ n+ n+ n+ n+ p+ p+ p+ p+ p+ p+ n-well n-well n-well n-well p substrate p substrate p substrate p substrate

  16. metal1 mask n+ n+ n+ n+ n+ n+ p+ p+ p+ p+ p+ p+ n-well n-well n-well n-well p substrate p substrate p substrate p substrate

  17. input rl GND VDD l l output R = = RS = R t w w w t w l n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  18. n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  19. n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  20. input GND VDD output n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  21. n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

  22. n+ n+ n+ p+ p+ p+ n-well n-well p substrate p substrate

More Related