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Work package 2

Work package 2. ASIC Building Blocks for SLHC ACEOLE Mid Term Review 3 rd August 2010 CERN – Geneva, Switzerland Paulo Moreira. People. ACEOLE fellow (ESR - 2 nd June 2009): José Pedro Cardoso Associated partner: INESC Porto / University of Porto Visiting Scientist:

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Work package 2

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  1. Work package 2 ASIC Building Blocks for SLHC ACEOLE Mid Term Review 3rd August 2010 CERN – Geneva, Switzerland Paulo Moreira

  2. People • ACEOLE fellow (ESR - 2nd June 2009): • José Pedro Cardoso • Associated partner: • INESC Porto / University of Porto • Visiting Scientist: • Dr. Jose Machado da Silva • CERN: • Work package leader: Paulo Moreira

  3. ASIC Building Blocks for SLHC • Development of Radiation-Hard ASIC building blocks • Low-Power, Low-Jitter VCXO based PLL • Specifications • Prototype development • Including design for testability and calibration • Functional and electrical characterization • Irradiation testing • Total Dose • Single Event Upsets • Final ASIC and Macro-cell • Characterization • Documentation • Technology: 130 nm CMOS • Low-noise 10 GHz VCO • Specifications • Modelling of radiation effects • Development of a radiation robust circuits • Integration of the macro-cell in the GBT10 ASIC • Technology: 90 nm CMOS

  4. Project Training Value • ASIC design skills • Analogue and communication circuit design knowledge • Training on CAE tools for ASIC design • Involvement in the full ASIC design cycle: • From specifications to production testing • Knowledge on radiation-tolerant design methodology • Design for testability methodologies • Training on radiation qualification tests procedures

  5. R&D work • Development of a Behavioural model for Phase-Locked Loop design • Design of a Jitter measurement circuit: ~1 ps resolution • Design of an Oscillator based on a Micro-Electro-Mechanical resonator • Current research project : design of a VCXO based PLL: • PLL features: • Automatic oscillation amplitude control • Digitally programmed oscillation amplitude and transconductance • Built In Self Tests Detailed technical reports and presentations can be found in: • https://espace.cern.ch/proj-gbt10/Reports/Forms/AllItems.aspx • https://espace.cern.ch/proj-gbt10/Presentations/Forms/AllItems.aspx

  6. Secondment • 1st Secondment period: • 2009/9/7 to 2010/4/1 • Partner: • INESC Porto, Portugal • (University of Porto, Portugal) • PhD in Electrical and Computer Engineering: • Seminar topics • Microelectronic and Microelectromechanical technologies • Test and Design for Testability • Digital Communications Systems • 2nd Secondment period: • 2011/02/25 to 2011/07/29 • Second semester of PhD studies

  7. Training • EPLF Course – “PLLs, VCOs and Frequency Synthesizers“ • 29th June to 1st July 2009, EPFL, Lausanne, Switzerland • ESSCIRC 2009 Conference • 14-18 September 2009, Athens, Greece • Short course: "Nanoscale CMOS analog design from devices to system" • At CERN: • Theoretical foundations: • Study of oscillators • Literature research (state of the art) • Topologies: LC and XTAL • Noise in oscillators • CADENCE tools training: • Full cycle: From schematics to extracted simulations • Integrated circuit design techniques: • Design and simulation (schematic and layout) of oscillators: • Single-ended • Differential • CERN’s course: “Leaders In Science”

  8. Training by Visiting Scientists • Dr. Jose Machado da Silva • 5th and 6th of February 2010: • “Test and Design for Testability of Analogue and Mixed-Signal Circuits” (6 H) • Course notes: http://indico.cern.ch/conferenceDisplay.py?confId=78641 • Dr. João Canas Ferreira • 25th and 26th 2010: • “Run-Time Reconfiguration of Hardware” (6 H) • Course notes: http://indico.cern.ch/conferenceDisplay.py?confId=78644

  9. Milestones and Deliverables [1] The nature of the deliverable is coded as follows: R = Report, P = Prototype, D = Demonstrator, O = Other [2] For research themes 1-5 the delivery dates are measured in months from the start of individual ESR contracts.

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