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How Computers Work. A brief review of EE306. Binary Representations. Unary Representation. “ One if by land, two if by sea ” (circa 1775) Three values for information: “land”, “sea”, “don’t know yet” Coded with 2 bits (No lights) — don’t know (One light) — by land
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How Computers Work A brief review of EE306
Unary Representation “One if by land, two if by sea” (circa 1775) • Three values for information: “land”, “sea”, “don’t know yet” • Coded with 2 bits • (No lights) — don’t know • (One light) — by land • (Two lights) — by sea • With n bits, code n+1 values
Binary Representation • Place value numbers systems date from roughly 3rd century BC (India). Modern decimal systems date from roughly 6th century AD. • Binary is the simplest possible place-value notation. • 10011 = 19
Addition in Binary • Just like regular arithmetic. Add each “bigit” and carry the 1s 011010 + 101011 1000101 26 43 69
Negative Numbers? • Use leftmost bit to indicate sign (called 1s compliment notation). • Leftmost bit equal 1 — negative. • Leftmost bit equal 0 — positive • Not efficient (two ways to encode zero) • Twos compliment notation • Compliment bits and add 1 to negate • -(0101) = (1010 + 1) = 1011
10 010100+1 = -21 001010+1 = -11 Addition is Easy in 2s Compliment • Just add normally, the sign will take care of itself! 001010 + 101011 110101
2s Compliment is Fixed Precision • Addition with negative numbers doesn’t always work out. Need to ignore carry out of last bigit position 011010 + 101011 1000101 26 -21 -59?
Overflow • In any fixed-precision encoding, overflow (or underflow) is a potential problem • Overflow — the result is too big to encode • Underflow — the result is too small to encode • In 2s compliment addition: • Overflow is not possible unless signs match • Otherwise, overflow/underflow occurs when result’s sign is different from operands sign
Computers • A computer consists of three things • Arithmetic and Logic Circuits • Memory • Control (sequencer) • First focus, basic operations • ADD • LOAD/STORE
Operands and the Register File • We need two source operands and one destination operand. • Our computer (the LC2) will allow each of these operands to be selected from one of eight “general purpose” registers. • The registers are essentially a small memory! • 16-bits wide (values -32768..+32767) • 8 registers means 3-bit “address” to select
16 16 16 The ALU • With a little extra logic, a 16-bit adder can be configured to perform multiple functions: AND, OR, NOT, NEGATE, etc. • ALUs are usually represented with the following symbol: OPA OPB 3 control F
Register File (8x16bits) 16 16 16 • Dual port the register file (just double the multiplexers) • Can read two registers and write back a register each cycle • A total of 13 control signals 3 WE/SEL Select A 3 4 Select B 3
What About Load/Store • To access memory, we need two quantities • Address • Value • Two special registers are used for this purpose • MAR (memory address register) • MDR (memory data register)
MDR Memory Path MAR 16-bit wide memory address Need 1 bit (“load”) control for each MAR/MDR Need 1 bit (“WE”) control for memory
Sequence For LOAD • Note that memory is always “ON”. We read memory by “latching” the values from the memory bus into MDR. • Load address into MAR • Latch memory contents into MDR • Latch MDR contents into register
Sequence for Store • Latch value into MDR • Latch address into MAR • Activate WE signal to memory
Data Bus • We frequently move data between • The ALU output • MDR or MAR • The register file • Let’s wire all these things together. • What if MDR is “1” when ALU is “0”? • We’ll put special switches on each output
Register File (8x16bits) 16 16 Tri-State Buffers Protect the Bus from conflicts 16-bit data bus MAR Added new control signals, one for each device that outputs to the bus MDR
Instructions and the PC • The brilliance of the Von Neumann design was the realization that programs could be stored in memory. • All of the operations the computer can do are encoded into an instruction. • Instructions are stored in memory (along with data). • The computer reads the instructions one at a time and edits them. • A special register (the PC) points to the next instruction that will be executed.
Instruction Fetch • When the computer is turned on, the first thing it does is fetch the next instruction: • PC is copied into MAR • MDR is latched (and holds the next instruction) • MDR’s contents are copied into a special register (IR) for safe keeping. • At the same time, the PC is incremented in preparation for the next instruction
Register File (8x16bits) 16 16 IR (used for control only) PC (a counter) MAR MDR
Decode • All of the possible instructions are encoded as a bit pattern • LC2 uses 16-bit instructions • 4 bits for “opcode” • The remaining 12 bits depend on the type of instruction • e.g., up to 9 bits specify source/destination operand registers
Instruction Format for ADD 15 • In principle, instruction formats are arbitrary. • In practice, the control logic is much easier to build if there is method to the madness • Similar positions in the instruction tend to mean similar things across instructions (ADD, AND, NOT, etc). 0 0001 dest SR1 000 SR2 not used Opcode
Execute ADD • Once IR has been loaded, execution takes only one more cycle • Connect SR1 and SR2 to SELA and SELB on register file • Send ALU the control signals to ADD. • Connect dest to WE/SEL on register file. • On next clock cycle, fetch the next instruction.
How Many Cycles to ADD? • ADD is perhaps the fastest instruction on the LC2. The datapath is optimized for this (and similar) instructions. • Still, it takes four full clock cycles: • Copy PC to MAR • Latch MDR • Latch IR • Add and latch result in register file
Calculating an Address • Our computer uses 16-bit addresses and 16-bit instructions. • Since four bits are used for the opcode, we have only 12 bits left. • At least 3 of those bits will specify the destination register (on load instructions) or source register (on store instructions). • How do we calculate a 16-bit address with only 9 bits? • PC relative addressing!
Direct Addressing Mode 15 0 • The address for a load instruction is formed by concatenating: • The 7 highest bits of the current PC • The 9 bits from the address field in the instruction • These 16 bits are written into MAR. 0010 dest 9 bits of address LD
How Many Cycles to Load? • As with ADD, it takes 3 cycles to load IR. • Once IR has been loaded, MAR can be loaded on the next cycle. • On the 5th cycle, MDR is written. • On the 6th cycle, the value from MDR is copied into the destination register.
Store Instructions • Similar instruction format as LD (different opcode). • 3 cycles to load IR • 4th cycle, load MAR • 5th cycle, load MDR (route through ALU by “adding 0”) • 6th cycle, write memory (turn on WE).
Writing a program • The program will compute the sum of three numbers and store the result in memory • First problem: where do we store the program? • How about beginning at location 0. • Next: where do we store the data? • Input data at locations 100-102 • Output data at location 103
Hexadecimal Notation • Binary is cumbersome • Decimal/Binary conversion is hard • Hexadecimal notation is base 16 • Use digits: 0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f • Hexadecimal/binary conversion is easy • 0x1234 = 0001 0010 0011 0100
The Program • Load location 100 into register 0 • Load location 101 into register 1 • Add register 0 and register 1 store result in register 0 (yes, we can do that) • Load location 102 into register 1 • Add register 0 and register 1, store result in register 0 (again) • Store register 0 in location 103
Other Instructions • From now on, we’ll use a C-like programming notation to describe each instruction. • We’ll refer to a memory location as M[x] • We’ll refer to a register as Rx • We’ll refer to numbers as #n • We’ll skip the instruction format (too hard to write machine code).
The AND Instruction • Synopsis: AND Rd, Rs1, Rs2 • Behavior: Rd = Rs1 & Rs2 • NOTES: • “&” is the C-language symbol for logical AND • Each bit of Rs1 is ANDed with the corresponding bit from Rs2, the result is written into Rd • Neither Rs1 nor Rs2 are changed (unless they’re the same as Rd)
ADD with Immediate • Synopsis: ADD Rd, Rs, #n • Behavior: Rd = Rs + n • NOTES: • n is a 5 bit 2s-compliment number • Related instructions • AND Rd, Rs, #n
LD/ST Instructions • Synopsis: LD Rd, #n • Behavior: • t = PC & 0xFE00 // zero out the 9 least bits • MA = t | n // OR t and n • Rd = M[MA] • NOTES • n is 9 bits • This is called the “direct” addressing mode • Related instructions • ST Rs, #n
Branch Instructions • A branch instruction loads a new value into the PC (instead of PC+1). • There are three 1-bit registers that are used for branch instructions • N, Z, P indicate if the last result was Negative, Zero or Positive respectively. • Set by every instruction that uses the ALU (e.g., AND, ADD, LD, ST, almost every instruction) • The branch instruction will load the PC only if the right combination of N, Z, and P are set to “1”.
Branch Instructions Continued • Synopsis: BRc #n • Behavior: (“c” is some combination of N,Z and P) • target = (PC & 0xFE00) | n // just like LD/ST • take = 0 • If (c includes “N”) take = take | N • If (c includes “Z”) take = take | Z • If (c includes “P”) take = take | P • If (take) PC = target // else PC = PC + 1 like normal • NOTES: n is 9 bits, if c is “NZP” are all set, the branch becomes “unconditional”
Calculating 2n • Location 100 holds N AND R0, R0, #0 // R0 = 0 ADD R0, R0, #1 // R0 = 1 LD R1, #100 // R1 = N Loop: BRz done // if N=0 stop ADD R0, R0, R0 // double R0 ADD R1, R1, #-1 // decr N BRnzp Loop // unconditional branch Done: ST R0, #101 // write result halt // stop the computer
Immediate Addressing Mode • Useful to put an address into a register • Synopsis: LEA Rd, #n • Behavior: • Rd = (PC & 0xFE00) | n • NOTE: address calculated just like direct addressing mode, but memory is not accessed.
Indexed Addressing Mode • Synopsis: LDR Rd, Rs, #n • Behavior: • MAR = Rs + n • Rd = M[MAR] • NOTES: • n must be positive and limited to 6 bits (0..63) • Related instructions • STR Rs1, Rs2, #n
Program to Sum a Vector • Size of Vector (N) is in loc 100, vector elements follow in locs 101…. AND R0, R0, #0 // R0 = 0 LEA R1, #101 // R1 = 101 LD R2, #100 // R2 = N Loop: BRz done LDR R3, R1, #0 // R1 holds address ADD R0, R0, R3 // calculate sum ADD R1, R1, #1 ADD R2, R2, #-1 BRnzp Loop Done: