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Data Dependence Types and Associated Pipeline Hazards

Data Dependence Types and Associated Pipeline Hazards. Sections 4.7. Type #1: Data Flow Dependence (True Dependence). InstrK reads operand written by InstrM Instr K is data dependent (aka true dependence) on Instr M Data must flow from instruction M to instruction K

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Data Dependence Types and Associated Pipeline Hazards

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  1. Data Dependence Types and Associated Pipeline Hazards Sections 4.7 Chapter 4 — The Processor — 1

  2. Type #1: Data Flow Dependence (True Dependence) • InstrKreads operand written by InstrM • InstrKis data dependent (aka true dependence) on InstrM • Data must flow from instruction M to instruction K • If two instructions are data dependent, they cannot execute simultaneously or be completely overlapped • Data dependence in an instruction sequence impliesdata dependence in source code • If data dependence caused a hazard in pipeline, it would be a RAW (Read After Write) hazard M: add $s0, $t0, $t1 K: sub $t2, $s0, $t3 CPE 432

  3. RAW Data Hazards • add$s0, $t0, $t1sub $t2, $s0, $t3 Chapter 4 — The Processor — 3

  4. N: sub r4,r1,r3 M: add r1,r2,r3 K: mul r6,r1,r7 Type #2: Name Dependence (Anti-dependence) • Name dependence is when 2 instructions (e.g. N and M) use the same register or memory location (called a name), but there is no flow of data between the instructions associated with that name • InstrM writes an operand that InstrNreads • Called an “anti-dependence” by compiler writers (we say that instruction N is data anti-dependant on instruction M)This results from the reuse of the name “r1” • If anti-dependence caused a hazard in the pipeline, it would be a Write After Read (WAR) hazard CPE 432

  5. DM DM Reg Reg Reg Reg IM IM ALU ALU Anti-dependence does NOT cause WAR Data Hazard in this pipeline CC0 CC1 CC2 CC3 CC4 CC6 CC7 CC8 CC5 add$t0,$t2,$t3 sub $s0,$t0,$t1

  6. N: sub r1,r4,r3 M: add r1,r2,r3 K: mul r6,r1,r7 Type #3: Name Dependence (Output dependence) • Instr M writes operand that Instr N writes. • Called an “output dependence” by compiler writersThis also results from the reuse of name “r1” • If outputdependance caused a hazard in the pipeline, it would be a Write After Write (WAW) hazard CPE 432

  7. Code Scheduling to Avoid Stalls • Reorder code to avoid use of load result in the next instruction • C code for A = B + E; C = B + F; Code Order 1# lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) stall stall 13 cycles Chapter 4 — The Processor — 7

  8. 2 Stalls: 13 Cycles Chapter 4 — The Processor — 8

  9. Code Scheduling to Avoid Stalls • Reorder code to avoid use of load result in the next instruction • C code for A = B + E; C = B + F; Code Order #2 lw $t1, 0($t0) lw $t2, 4($t0) lw $t4, 8($t0) add $t3, $t1, $t2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 11 cycles Chapter 4 — The Processor — 9

  10. Reodering of Code; No Hazards: 11 Cycles lw $t2, 4($t0) lw $t4, 8($t0) add $t3,$t1,$t2 add $t5, $t1,$t4 Chapter 4 — The Processor — 10

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