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Pipeline Control Hazards and Instruction Variations

This lecture material from CS 3410 at Cornell University discusses control hazards and instruction variations within pipelined processor architectures. Key topics include the handling of control hazards, branch prediction, and stall mechanisms as well as instruction variations specific to ARM and x86 architectures. By understanding these concepts, students learn how to optimize instruction execution and minimize delay in pipelines. Resources, assignment deadlines, and exam dates are also provided for students to utilize during their studies.

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Pipeline Control Hazards and Instruction Variations

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  1. Pipeline Control Hazardsand Instruction Variations Hakim Weatherspoon CS 3410, Spring 2011 Computer Science Cornell University See P&H Appendix4.8 & 2.16 and 2.17

  2. Announcements PA1 available: mini-MIPS processor • PA1 due next Friday • Work in pairs • Use your resources • FAQ, class notes, book, Sections, office hours, newsgroup, CSUGLab • Prelims: • Thursday, March 10thin class • Thursday, April 28th Evening

  3. Goals for Today • Recap: Data Hazards • Control Hazards • What is the next instruction to execute if a branch is taken? Not taken? • How to resolve control hazards • Optimizations • Instruction Variations • ARM • x86

  4. Data Hazard Recap • Delay Slot(s) • Modify ISA to match implementation • Stall • Pause current and all subsequent instructions • Forward/Bypass • Try to steal correct value from elsewhere in pipeline • Otherwise, fall back to stalling or require a delay slot

  5. More Hazards A instmem D B datamem PC +4

  6. More Hazards A instmem D B datamem PC +4

  7. Control Hazards • Control Hazards • instructions are fetched in stage 1 (IF) • branch and jump decisions occur in stage 3 (EX) • i.e. next PC is not known until 2 cycles after branch/jump • Delay Slot • ISA says N instructions after branch/jump always executed • MIPS has 1 branch delay slot • Stall (+ Zap) • prevent PC update • clear IF/ID pipeline register • instruction just fetched might be wrong one, so convert to nop • allow branch to continue into EX stage

  8. Delay Slot A instmem D B datamem PC branchcalc +4 decidebranch

  9. Control Hazards: Speculative Execution • Control Hazards • instructions are fetched in stage 1 (IF) • branch and jump decisions occur in stage 3 (EX) • i.e. next PC not known until 2 cycles after branch/jump • Stall • Delay Slot • Speculative Execution • “Guess” direction of the branch • Allow instructions to move through pipeline • Zap them later if wrong guess • Useful for long pipelines

  10. Loops

  11. Branch Prediction

  12. Branch Prediction

  13. Pipelining: What Could Possibly Go Wrong? • Data hazards • register file reads occur in stage 2 (IF) • register file writes occur in stage 5 (WB) • next instructions may read values soon to be written • Control hazards • branch instruction may change the PC in stage 3 (EX) • next instructions have already started executing • Structural hazards • resource contention • so far: impossible because of ISA and pipeline design

  14. Goals for Today • Recap: Data Hazards • Control Hazards • What is the next instruction to execute if a branch is taken? Not taken? • How to resolve control hazards • Optimizations • Instruction Variations • ARM • x86

  15. Variations • More shifts

  16. Variations • Condition flags

  17. Variations • Condition flags

  18. Variations • Condition flags

  19. Variations • Conditional instructions • top: CMP r3, r4 • SUBGT r3, r3, r4 • SUBLT r4, r4, r3 • BNE top

  20. Variations • Stack operations & multiple destinations

  21. Variations • String instructions • MOV AX, FFh • MOV DI, 5000h • MOV CX, 2000h • REP STOSB

  22. Variations • Vector instructions • vaddubs v3, v1, v2

  23. Next time • Instruction Variations • ARM/MIPS (RISC) • Versus x86 (CISC)

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