1 / 14

TLM Signal A non-memory mapped bus model

TLM Signal A non-memory mapped bus model . Presenter: R Swaminathan Authors: R. Swaminathan , Vishal Goel Company/Organization: Texas Instruments. Agenda. Introduction Prior Art Why tlm_signal ? TLM2 Interoperability Layer Customizing Payload Customizing Interfaces

tessa
Download Presentation

TLM Signal A non-memory mapped bus model

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. TLM Signal A non-memory mapped bus model Presenter: R Swaminathan Authors: R. Swaminathan, Vishal Goel Company/Organization: Texas Instruments

  2. Agenda • Introduction • Prior Art • Why tlm_signal? • TLM2 Interoperability Layer • Customizing Payload • Customizing Interfaces • Customizing Sockets • Example: Level Interrupt Convenience Socket • Sequence Diagram • Conclusions • References • Acknowledgements

  3. Introduction • TLM 2.0 has enjoyed wide success in standardizing memory mapped bus protocol handling. • AXI, OCP etc • Unfortunately there are many signals that are yet enjoy the benefits of standardization like: • Reset • Interrupts (edge and level) • Power interfaces • IO Pins • Endian • … Hardware Model Memory Mapped Buses Configuration Interrupts Stimulation Monitoring & Analysis Clocks Resets and Power Supply Debugger Sim kernel Interaction - Representations of Hardware IFs IFs for Simulation Only Package

  4. Prior Art • sc_in/sc_out/sc_signal<bool> - OSCI • Delta cycle delay • Low level hardware semantics • Signal Socket - GreenSocs • Feature rich, but needs supporting GreenSocs infrastructure like GreenSocket etc. • sc_wire – Cadence/ST Microelectronics • Does away with delta-cycle delay • Does not support optional extensions (based on TLM1.0)

  5. Why tlm_signal? • No delta cycle delay to transport values across • Data value typically bool, but should be customizable for other data-types too. • Should permit optional payload values to carry useful attributes and/or debug information • Leverage the benefits of TLM2 standard (through reuse) • TLM base communication protocol • TLM extensions • TLM error codes • Performance (memory manager)

  6. TLM2 Interoperability Layer 2. Core interfaces and sockets Customize Initiator Target Customize Customize 1. Generic Payload 3. Base Protocol Command Address Data Byte Enables Response Status BEGIN_REQ END_REQ BEGIN_RESP Extensions END_RESP

  7. Customize Payload tlm2 Customization tlm_signal • Drop • Drop non-signal related attributes like addr, byte_en, stream_width, data_ptr etc. • Add • Templatized payload with Signal type (default to bool) and add access functions to set/get signal • Restrict • tlm_command: TLM_WRITE_COMMAND, TLM_IGNORE_COMMAND. • tlm_response_status: TLM_OK_RESPONSE, TLM_COMMAND_ERROR_REPONSE, TLM_INCOMPLETE_RESPONSE, TLM_GENERIC_ERROR_REPONSE • Reuse • Everything else like memory manager, extensions etc. 1. Generic Payload tlm_signal_gp<SIG=bool> Command Address Data Byte Enables Response Status Command signal: SIG Response Status template<typename SIG=bool> structtlm_signal_base_protocol_types { typedef SIG tlm_signal_type; typdeftlm_signal_gp<tlm_signal_type> tlm_payload_type; typedeftlm_phasetlm_phase_type; }; structtlm_base_protocol_types { typdefgeneric_payloadtlm_payload_type; typedeftlm_phasetlm_phase_type; }; traits Extensions Extensions

  8. Customize Interfaces 2. Core interfaces and sockets Initiator Target class tlm_fw_transport_if class tlm_signal_fw_transport_if tlm2 tlm_signal Customization b_transport nb_transport_fw get_direct_mem_ptr transport_dbg b_transport nb_transport_fw • Drop • tlm_fw_direct_mem_if, tlm_bw_direct_mem_if, tlm_transport_dbg_if • Change • Instead of TYPES being templatized on tlm_base_protocol_types, these are now templatized on tlm_signal_base_protocol_types<>. • Reuse • Semantics • Phase restricted to BEGIN_REQ and END_REQ class tlm_bw_transport_if class tlm_signal_bw_transport_if nb_transport_bw invalidate_direct_mem_ptr nb_transport_bw

  9. Customize Sockets tlm_base_initiator_socket <BW, FW_IF, BW_IF, N, POL> tlm2 tlm_signal tlm_initiator_socket <BW,TYPES= tlm_base_protocol_types, N, POL> : tlm_base_initator_socket<BW, tlm_fw_transport_if<TYPES>, tlm_bw_transport_if<TYPES, N, POL> tlm_signal_initiator_socket <SIG=bool,TYPES= tlm_signal_base_protocol_types<SIG>, N, POL> : tlm_base_initiator_socket<0, tlm_signal_fw_transport_if<TYPES>, tlm_signal_bw_transport_if<TYPES>, N, POL> tlm_base_target_socket <BW, FW_IF, BW_IF, N, POL> tlm_target_socket <BW,TYPES= tlm_base_protocol_types, N, POL> : tlm_base_target_socket<BW, tlm_fw_transport_if<TYPES>, tlm_bw_transport_if<TYPES, N, POL> tlm_signal_target_socket <SIG=bool,TYPES= tlm_signal_base_protocol_types<SIG>, N, POL> : tlm_base_target_socket<0, tlm_signal_fw_transport_if<TYPES>, tlm_signal_bw_transport_if<TYPES>, N, POL>

  10. Example: Level Interrupt Convenience Socket Initiator Target • Simplified interfaces • Initiator calls set_interrupt(active=true/false) and target handles the same. • Ease of integration • Integrator does not have to bother about conversions between active-high/active-low connections. • If such information is required, it may be captured as attributes of sockets and interpreted accordingly. • Extensibility • If this utility socket needs to be connected to some IP that needs such information, it may be communicated via extensions. level_interrupt_target +register_interrupt_cb(cb_type): void +prop: sc_attr_cltn typedef boost::function<void(bool)>cb_type; level_interrupt_initiator +set_interrupt(active:bool) +prop: sc_attr_cltn Extensions Extensions

  11. Sequence Diagram Initiator (convenience) Target (convenience) handle_interrupt(bool active) w/o ack set_interrupt(true) nb_transport_fw(sig_gp, BEG_REQ,delay) :TLM_COMPLETED handle_interrupt(bool active) set_interrupt(true) nb_transport_fw(sig_gp, BEG_REQ,delay) w/ ack :TLM_ACCEPTED nb_transport_bw(sig_gp, END_REQ,delay) send_ack() handle_ack() :TLM_COMPLETED

  12. Conclusions • tlm_signal presents a minimal set of TLM2 payload/interfaces selected to achieve the required functionality. • It also offers reduced learning curve as TLM2 semantics is reused to large extent. • There is a need to standardize on the non-memory mapped bus signals, and tlm_signal is presented as a candidate towards achieving the same.

  13. References • SystemC Reference Manual - Accellera • sc_wire– Cadence/ST Microelectronics • SignalSocket– GreenSocs

  14. Acknowledgements • Anonymous reviewers of the ISCUG Abstract for their many insightful comments. • Tor Jeremiassen, Amit Nene and Nizamudheen A, Texas Instruments, for their providing their valuable inputs on this presentation.

More Related