Lab 2 Basic Gates in a PLD. Module M2.3 Section 4.2 Experiment 2 (p. 63). Experiment 2. CUPL Header. CUPL Comments. CUPL Inputs and Outputs. CUPL Logic Equations. CUPL Chip Diagram in .DOC File. Fuse Plot for !X. Structure of the GAL 16V8 PLD. Fuse Plot for !Y.
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Experiment 2 (p. 63)
closed B = 0 C = A
open B = 1
C = !A