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This progress report outlines the work done by Yung-Chih Chen on the synthesis of SET arrays using BDD-based techniques and the implementation of threshold logic gates. The report covers topics such as node merging, node addition and removal, bounded sequential equivalence checking (BSEC), and circuit unrolling for miter construction in SAT-based sequential equivalence checking. The emphasis is on speeding up the process and achieving accurate experimental results. Ongoing research includes automated mapping for SET arrays, handling single and multiple outputs, partitioning, threshold logic rewirement, and equivalence checking for threshold logic implementation using SET arrays.
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Progress report Yung-Chih Chen
Done Current detector • Synthesis for BDD-based SETarrays a f = a’b’+ab 00 11 b b 1 0 1 Boolean function BDD Product term SET array
Ongoing • Threshold logic gate implementation by using a BDD-based SET array a b c d 3 2 1 1 1 f High Low a b c d Short Open
Threshold logic network T w w w w T w w w w T w w w w T w w w w
SETarray partition Conventional logic network Threshold logic network
Done • Node merging • Node addition and removal A A B B A A B B C
Application • Bounded Sequential Equivalence Checking (BSEC) • unroll circuits → construct a miter → SAT PI PI PI PI F F F F S0 . . . G G G G PO PO PO PO . . . T=0 T=1 1 T=n-1 T=n
F F F F . . . G G G G Ongoing • Speed up SAT-based sequential equivalence checking
Current flow Miter Unrolling F F0 Fn NM/NAR . . . G G0 Gn PO PO PO
Project • Automated mapping for SET arrays • Single output • Multiple outputs • Partition • Threshold logic • Rewiring • Equivalence checking • Threshold logic implementation by using SET arrays