VLSI Implementation of Threshold Logic – A Comprehensive Survey

Authors: Valeriu Beiu, Jose M. Quintana, and Maria J. Aedillo Speaker: Chia-Chun Lin 2012/3/23 VLSI Implementation of Threshold Logic – A Comprehensive Survey

Outline • CMOS-compatible solutions • Capacitive Implementation • Conductance/Current Implementation • Other Implementations • Conclusion

CMOS-compatible Solutions • First pure CMOS solution (1975) • The CMOS devices have MAJORITY logic functions with near-symmetrical switching delay times. • Characteristic • low power consumption • large noise margins • larger fan-in are slow

CMOS-compatible Solutions • NULL convention logic (1997) • Characteristic • low power consumption • large noise margins • fast for small fan-ins

CMOS-compatible Solutions • NULL convention logic (1997) • ex. The output Z will be asserted when: • Input A1…An are asserted. • Any combination of the inputs A1…An are asserted and the output Z wasasserted. • Any one of the inputs A1…Anis asserted and the output Z wasasserted.

CMOS-compatible Solutions • Pass-transistor logic (2001) • Tally circuit

CMOS-compatible Solutions • Pass-transistor logic (2001) • Characteristic • depend on the number of variables, not on their associated weights x1 x2 X3 X4 K 1 1 2 2 f

Capacitive Implementation • Switched Capacitor (1987) • Characteristic • High power consumption • large delay • large area • large fan-in capability

Capacitive Implementation • Neuron-MOS transistor • An ordinary MOSFET except using the potential of floating gates to determine the on/off state of the transistor.

Capacitive Implementation • Neuron-MOS transistor • Characteristic • simple and compact • sensitivity to parasiticalcharges • sensitivity to process variation • UV light erasure is required • high power consumption

Conductance/Current • Pseudo-nMOS • Uses only one pMOS as a constant load. • The ration rules make it possible to implement TLFs. • Characteristic • fast • large fan-in • susceptible to noise • high power consumption

Conductance/Current • Output-wired Inverter (1973) • Based on a plurality of inverters with their output hard wired together. • Characteristic • fast • limited fan-in • narrow noise margins • high power consumption

Other Implementations • Single Electron Tunneling (SET) • Many use a capacitor array for input summation • Characteristic • large integration • ultra-low power dissipation

Other Implementations • Resonant Tunneling Devices (RTDs) • Negative Differential Resistance (NDR) load driver

Conclusion • The nanotechnologies, e.g. RTDs, SET, appear to hold the most promise as a short-to-medium-term solution. • As RTDs are already operating at room temperature (as apposed to SET). The fact that TL is a perfect fit for RTDs will certainly help.

PDN

VLSI Implementation of Threshold Logic – A Comprehensive Survey