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REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS

REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS. ELEC 6270 Kannan Govindasamy. OUTLINE. Objective Simulation Specification Background information Implementation Results Conclusion. OBJECTIVE. Design and Verify a 32 bit Shift Register with Multi-phase Clocks

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REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS

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  1. REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS ELEC 6270 Kannan Govindasamy

  2. OUTLINE • Objective • Simulation Specification • Background information • Implementation • Results • Conclusion

  3. OBJECTIVE • Design and Verify a 32 bit Shift Register with Multi-phase Clocks • Study Low Voltage Power and Delay characteristics

  4. Simulation Specification

  5. Dynamic Signal transitions Logic activity Glitches Short-circuit Static Leakage Background Information

  6. Shift Registers with Multiphase clocks

  7. Multiphase Clock Generators Modified Johnson counter is used for Multiphase Clock generation

  8. ELDO SIMULATION

  9. Results Power Table N=1

  10. Results Power Table N=4

  11. Results Delay Table for N=1

  12. Power vs Voltage

  13. Delay vs Voltage Plot

  14. Power-Delay Plot

  15. Power Consumption vs Parallelism

  16. Summary • A power reduction of 39.1% is achieved when degree of parallelism is 4. • A power reduction of 45.07% is achieved for N=8. for further parallelism power reduction gets stabilized

  17. Reference • ELEC 6270 class slides by Dr.Agrawal • Tsung-chu Huang, Kuen-Jong Lee, A Low-Power LFSR Architecture, Test symposium 2001

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