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Pertemuan 23 Basic Processing Unit: I PowerPoint Presentation
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Pertemuan 23 Basic Processing Unit: I

Pertemuan 23 Basic Processing Unit: I

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Pertemuan 23 Basic Processing Unit: I

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  1. Pertemuan 23Basic Processing Unit: I Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1

  2. Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : • Mendesain microprogramming untuk instruksi Microprocessor ( C5 ) ( No TIK : 11 )

  3. Chapter 7. Basic Processing Unit: I

  4. Internal processor b us R i in R i R i out Y in Y Constant 4 Select MUX A B ALU Z in Z Z out Figure 7.2. Input and output gating for the registers in Figure 7.1.

  5. Figure 7.3. Input and output gating for one register bit.

  6. Figure 7.4. Connection and control signals for register MDR.

  7. Step Action 1 PC , MAR , Read, Select4, Add, Z in in out 2 Z , PC , Y , WMF C out in in 3 MDR , IR out in 4 Offset-field-of-IR , Add, Z out in 5 Z , PC , End in out Figure 7.7. Control sequence for an unconditional branch instruction.

  8. Step Action 1 PC , R=B, MAR , Read, IncPC out in 2 WMF C 3 MDR , R=B, IR in outB 4 R4 , R5 , SelectA, Add, R6 , End outA outB in Figure 7.9. Control sequence for the instruction. Add R4,R5,R6, for the three-bus organization in Figure 7.8.

  9. CLK Control step Clock counter External inputs Decoder/ IR encoder Condition codes Control signals Figure 7.10. Control unit organization.

  10. Pertemuan 1Basic Processing Unit: II Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1

  11. Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : • Mendesain microprogramming untuk instruksi Microprocessor ( C5 ) ( No TIK : 11 )

  12. Chapter 7. Basic Processing Unit: II

  13. Branch Add T T 4 6 T 1 Figure 7.12. Generation of the Zincontrol signal for the processor in Figure 7.1.

  14. Address Microinstruction 0 PC , MAR , Read, Select4, Add, Z in in out 1 Z , PC , Y , WMF C out in in 2 MDR , IR out in 3 Branch to starting address of appropriate microroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 If N=0, then branch to microinstruction 0 26 Offset-field-of-IR , SelectY, Add, Z out in 27 Z , PC , End out in Figure 7.17. Microroutine for the instruction Branch<0.

  15. Mode Contents of IR OP code 0 1 0 Rsrc Rdst 11 10 8 7 4 3 0 Address Microinstruction (octal) 000 PC , MAR , Read, Select , Add, Z 4 in in out 001 Z , PC , Y , WMFC out in in 002 MDR , IR out in 003 Branch { PC 101 (from Instruction decoder); m m ¬ PC [IR ]; PC [IR ] × [IR ] × [IR ]} m ¬ m ¬ 10 9 8 5,4 10,9 3 121 Rsrc , MAR , Read, Select4, Add, Z in out in 122 Z , Rsrc out in ¬ ¬ 123 m Branch { m PC 170; m PC [IR ]}, WMFC 0 8 170 MDR , MAR , Read, WMFC out in 171 MDR , Y out in 172 Rdst , SelectY , Add, Z in out 173 Z , Rdst , End out in Figure 7.21. Microinstruction for Add (Rsrc)+,Rdst. Note: Microinstruction at location 170 is not executed for this addressing mode.

  16. Figure P7.1. Organization of shift-register control for Problem 7.22.

  17. Clock X A Y B Z Figure P7.2.Digital controller in Problem 7.23.