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Problems with Superscalar approach. Limits to conventional exploitation of ILP: 1) Pipelined clock rate : Each increase in clock rate has corresponding CPI increase (branches, other hazards). (pipeline latency)

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## Problems with Superscalar approach

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**Problems with Superscalar approach**• Limits to conventional exploitation of ILP: 1) Pipelined clock rate: Each increase in clock rate has corresponding CPI increase (branches, other hazards). (pipeline latency) 2) Instruction fetch and decode: At some point, its hard to fetch and decode more instructions per clock cycle. (ILP) 3) Cache hit rate: Some long-running (scientific) programs have very large data sets accessed with poor locality; others have continuous data streams (multimedia) and hence poor locality. (memory latency).**X86 CPU Cache/Memory Performance Example:AMD Athlon T-Bird**Vs. Intel PIII, Vs. P4 AMD Athlon T-Bird 1GHZ L1: 64K INST, 64K DATA (3 cycle latency), both 2-way L2: 256K 16-way 64 bit Latency: 7 cycles L1,L2 on-chip Intel P4 utilizes PC800 bandwidth much better than PIII due to P4’s higher 400MHZ FSB. Intel P 4, 1.5 GHZ L1: 8K INST, 8K DATA (2 cycle latency) both 4-way 96KB Execution Trace Cache L2: 256K 8-way 256 bit , Latency: 7 cycles L1,L2 on-chip Intel PIII 1 GHZ L1: 16K INST, 16K DATA (3 cycle latency) both 4-way L2: 256K 8-way 256 bit , Latency: 7 cycles L1,L2 on-chip Source: http://www1.anandtech.com/showdoc.html?i=1360&p=15 From 551**Increasing Instruction-Level Parallelism**• A common way to increase parallelism among instructions is to exploit parallelism among iterations of a loop • (i.e Loop Level Parallelism, LLP). • This is accomplished by unrolling the loop either statically by the compiler, or dynamically by hardware, which increases the size of the basic block present. • In this loop every iteration can overlap with any other iteration. Overlap within each iteration is minimal. for (i=1; i<=1000; i=i+1;) x[i] = x[i] + y[i]; • In vector machines, utilizing vector instructions is an important alternative to exploit loop-level parallelism, • Vector instructions operate on a number of data items. The above loop would require just four such instructions. From 551**Loop-Level Parallelism (LLP) Analysis**• LLP analysis is normally done at the source level or close to it since assembly language and target machine code generation introduces a loop-carried dependence, in the registers used for addressing and incrementing. • Instruction level parallelism (ILP) analysis is usually done when instructions are generated by the compiler. • Analysis focuses on whether data accesses in later iterations are data dependent on data values produced in earlier iterations. e.g. in for (i=1; i<=1000; i++) x[i] = x[i] + s; the computation in each iteration is independent of the previous iterations and the loop is thus parallel. The use of X[i] twice is within a single iteration. From 551**LLP Analysis Examples**• In the loop: for (i=1; i<=100; i=i+1) { A[i+1] = A[i] + C[i]; /* S1 */ B[i+1] = B[i] + A[i+1];} /* S2 */ } • S1 uses a value computed in an earlier iteration, since iteration i computes A[i+1] read in iteration i+1 (loop-carried dependence, prevents parallelism). • S2 uses the value A[i+1], computed by S1 in the same iteration (not loop-carried dependence). From 551**LLP Analysis Examples**• In the loop: for (i=1; i<=100; i=i+1) { A[i] = A[i] + B[i]; /* S1 */ B[i+1] = C[i] + D[i]; /* S2 */ } • S1 uses a value computed by S2 in a previous iteration (loop-carried dependence) • This dependence is not circular (neither statement depend on itself; S1 depends on S2 but S2 does not depend on S1. • Can be made parallel by replacing the code with the following: A[1] = A[1] + B[1]; for (i=1; ii<=99; i=i+1) { B[i+1] = C[i] + D[i]; A[i+1] = A[i+1] + B[i+1]; } B[101] = C[100] + D[100]; From 551**A[1] = A[1] + B[1];**B[2] = C[1] + D[1]; A[99] = A[99] + B[99]; B[100] = C[99] + D[99]; A[2] = A[2] + B[2]; B[3] = C[2] + D[2]; A[100] = A[100] + B[100]; B[101] = C[100] + D[100]; LLP Analysis Example for (i=1; i<=100; i=i+1) { A[i] = A[i] + B[i]; /* S1 */ B[i+1] = C[i] + D[i]; /* S2 */ } Original Loop: Iteration 99 Iteration 100 Iteration 1 Iteration 2 . . . . . . . . . . . . Loop-carried Dependence • A[1] = A[1] + B[1]; • for (i=1; i<=99; i=i+1) { • B[i+1] = C[i] + D[i]; • A[i+1] = A[i+1] + B[i+1]; • } • B[101] = C[100] + D[100]; Modified Parallel Loop: Iteration 98 Iteration 99 . . . . Iteration 1 Loop Start-up code A[1] = A[1] + B[1]; B[2] = C[1] + D[1]; A[99] = A[99] + B[99]; B[100] = C[99] + D[99]; A[2] = A[2] + B[2]; B[3] = C[2] + D[2]; A[100] = A[100] + B[100]; B[101] = C[100] + D[100]; Not Loop Carried Dependence Loop Completion code From 551**SCALAR**(1 operation) VECTOR (N operations) v2 v1 r2 r1 + + r3 v3 vector length addv.d v3, v1, v2 Add.d F3, F1, F2 Alternative Model:Vector Processing • Vector processors have high-level operations that work on linear arrays of numbers: "vectors"**Vectors vs. Single-issue Scalar**Vector • One instruction fetch,decode, dispatch per vector • Structured register accesses • Smaller code for high performance, less power in instruction cache misses • Bypass cache • One TLB lookup pergroup of loads or stores • Move only necessary dataacross chip boundary • Single-issue Scalar • One instruction fetch, decode, dispatch per operation • Arbitrary register accesses,adds area and power • Loop unrolling and software pipelining for high performance increases instruction cache footprint • All data passes through cache; waste power if no temporal locality • One TLB lookup per load or store • Off-chip access in whole cache lines**Vector vs. Superscalar**Vector • Control logic growslinearly with issue width • Vector unit switchesoff when not in use • Vector instructions expose parallelism without speculation • Software control ofspeculation when desired: • Whether to use vector mask or compress/expand for conditionals • Superscalar • Control logic grows quad-ratically with issue width • Control logic consumes energy regardless of available parallelism • Speculation to increase visible parallelism wastes energy**Properties of Vector Processors**• Each result in a vector operation is independent of previous results => long pipelines used, compiler ensures no dependencies=> higher clock rate • Vector instructions access memory with known pattern=> highly interleaved memory with multiple banks used.=> amortize memory latency of over 64 elements => no (data) caches required! (Do use instruction cache) • Reduces branches and branch problems in pipelines • Single vector instruction implies lots of work ( loop) => fewer instruction fetches**Changes to scalar processor to run vector instructions**• Decode vector instructions. • Send scalar registers to vector unit (vector-scalar ops). • Synchronization for results back from vector register, including exceptions. • Things that don’t run in vector don’t have high ILP, so can make scalar CPU simple.**Spec92fp Operations (Millions) Instructions (M)**Program RISC Vector R / V RISC Vector R / V swim256 115 95 1.1x 115 0.8 142x hydro2d 58 40 1.4x 58 0.8 71x nasa7 69 41 1.7x 69 2.2 31x su2cor 51 35 1.4x 51 1.8 29x tomcatv 15 10 1.4x 15 1.3 11x wave5 27 25 1.1x 27 7.2 4x mdljdp2 32 52 0.6x 32 15.8 2x Operation & Instruction Count: RISC v. Vector Processor Vector reduces ops by 1.2X, instructions by 20X**Basic Vector Architecture**• A vector processor typically consists of an ordinary pipelined scalar unit plus a vector unit. • The scalar unit is basically no different advanced pipelined CPUs, commercial vector machines have included both out-of-order scalar units (NEC SX/5) and VLIW scalar units (Fujitsu VPP5000). • Types of architecture for vector processors: • Memory-memory vector processors: all vector operations are memory to memory • Vector-register processors: all vector operations between vector registers (except load and store) • Vector equivalent of load-store architectures • Includes all vector machines since late 1980s: Cray, Convex, Fujitsu, Hitachi, NEC • We assume vector-register for rest of lecture**Components of Vector Processor**• Vector Register: fixed length bank holding a single vector • has at least 2 read and 1 write ports • typically 8-32 vector registers, each holding 64-128 64-bit elements • Vector Functional Units (FUs): fully pipelined, start new operation every clock • typically 4 to 8 FUs: FP add, FP mult, FP reciprocal (1/X), integer add, logical, shift; may have multiple of same unit • Vector Load-Store Units (LSUs): fully pipelined unit to load or store a vector; may have multiple LSUs • Scalar registers: single element for FP scalar or address • Cross-bar to connect FUs , LSUs, registers**Vector Linpack Performance (MFLOPS)**Machine Year Clock 100x100 1kx1k Peak(Procs) • Cray 1 1976 80 MHz 12 110 160(1) • Cray XMP 1983 120 MHz 121 218 940(4) • Cray YMP 1988 166 MHz 150 307 2,667(8) • Cray C-90 1991 240 MHz 387 902 15,238(16) • Cray T-90 1996 455 MHz 705 1603 57,600(32) • Conv. C-1 1984 10 MHz 3 -- 20(1) • Conv. C-4 1994 135 MHz 160 2531 3240(4) • Fuj. VP200 1982 133 MHz 18 422 533(1) • NEC SX/2 1984 166 MHz 43 885 1300(1) • NEC SX/3 1995 400 MHz 368 2757 25,600(4)**How To Pick Vector Length?**• Longer good because: 1) Hide vector startup 2) lower instruction bandwidth 3) tiled access to memory reduce scalar processor memory bandwidth needs 4) if know max length of app. is < max vector length, no strip mining overhead 5) Better spatial locality for memory access • Longer not much help because: 1) diminishing returns on overhead savings as keep doubling number of element 2) need natural app. vector length to match physical register length, or no help**How To Pick Number of Vector Registers?**• More Vector Registers: 1) Reduces vector register “spills” (save/restore) • 20% reduction to 16 registers for su2cor and tomcatv • 40% reduction to 32 registers for tomcatv • others 10%-15% 2) aggressive scheduling of vector instructinons: better compiling to take advantage of ILP • Fewer: Fewer bits in instruction format (usually 3 fields)**Vector Implementation**• Vector register file: • Each register is an array of elements • Size of each register determines maximumvector length (MVL) supported. • Vector length register (VLR) determines vector lengthfor a particular operation • Multiple parallel execution units = “lanes”(sometimes called “pipelines” or “pipes”)**Using multiple functional units to improve the performance**of a single vector add instruction (a) has a single add pipeline and can complete one addition per cycle. The machine shown in (b) has four add pipelines and can complete four additions per cycle.**Vector Memory operations**• Load/store operations move groups of data between registers and memory • Three types of addressing • Unit stride • Fastest • Non-unit(constant) stride • Indexed (gather-scatter) • Vector equivalent of register indirect • Good for sparse arrays of data • Increases number of programs that vectorize**DAXPY (Y = a*X + Y)**Assuming vectors X, Y are length 64 Scalar vs. Vector L.D F0,a ;load scalar a LV V1,Rx ;load vector X MULVS.D V2,V1,F0 ;vector-scalar mult. LV V3,Ry ;load vector Y ADDV.D V4,V2,V3 ;add SV Ry,V4 ;store the result L.D F0,a DADDIU R4,Rx,#512 ;last address to load loop: L.D F2, 0(Rx) ;load X(i) MUL.D F2,F0,F2 ;a*X(i) L.D F4, 0(Ry) ;load Y(i) ADD.D F4,F2, F4 ;a*X(i) + Y(i) S.D F4,0(Ry) ;store into Y(i) DADDIU Rx,Rx,#8 ;increment index to X DADDIU Ry,Ry,#8 ;increment index to Y DSUBU R20,R4,Rx ;compute bound BNEZ R20,loop ;check if done 578 (2+9*64) vs. 321 (1+5*64) ops (1.8X) 578 (2+9*64) vs. 6 instructions (96X) 64 operation vectors + no loop overhead also 64X fewer pipeline hazards**1: LV V1,Rx ;load vector X**2: MULV V2,F0,V1 ;vector-scalar mult. LV V3,Ry ;load vector Y 3: ADDV V4,V2,V3 ;add 4: SV Ry,V4 ;store the result Vector Execution Time • Time = f(vector length, data dependicies, struct. Hazards, C) • Initiation rate: rate that FU consumes vector elements.(= number of lanes; usually 1 or 2 on Cray T-90) • Convoy: set of vector instructions that can begin execution in same clock (no struct. or data hazards) • Chime: approx. time for a vector element operation (~ one clock cycle). • m convoys take m chimes; if each vector length is n, then they take approx. m x n clock cycles (ignores overhead; good approximization for long vectors) 4 conveys, 1 lane, VL=64 => 4 x 64 256 clocks (or 4 clocks per result)**Vector FU Start-up Time**• Start-up time: pipeline latency time (depth of FU pipeline); another sources of overhead • Operation Start-up penalty (from CRAY-1) • Vector load/store 12 • Vector multiply 7 • Vector add 6 Assume convoys don't overlap; vector length = n: Convoy Start 1st result last result 1. LV 0 12 11+n (12+n-1) 2. MULV, LV 12+n 12+n+12 23+2n Load start-up 3. ADDV 24+2n 24+2n+6 29+3n Wait convoy 2 4. SV 30+3n 30+3n+12 41+4n Wait convoy 3**Vector Loop Processing**• Use vectors for inner loop parallelism (LLP): • One dimension of array: A[0, 0], A[0, 1], A[0, 2], ... • think of machine as, say, 32 vector regs each with 64 elements • 1 instruction updates 64 elements of 1 vector register • and for outer loop parallelism: • 1 element from each column: A[0,0], A[1,0], A[2,0], ... • think of machine as 64 “virtual processors” (VPs) each with 32 scalar registers ( multithreaded processor) • 1 instruction updates 1 scalar register in 64 VPs • Hardware identical, just 2 compiler perspectives**Virtual Processor Vector Model**• Vector operations are SIMD (single instruction multiple data) operations. • Each element is computed by a virtual processor (VP) • Number of VPs given by vector length: • vector control register.**Virtual Processors ($vlr)**VP0 VP1 VP$vlr-1 General Purpose Registers vr0 Control Registers vr1 vr31 vcr0 vcr1 $vdw bits vf0 Flag Registers (32) vf1 vcr31 32 bits vf31 1 bit Vector Architectural State**Vector Load/Store Units & Memories**• Start-up overheads usually longer for LSUs • Memory system must sustain (# lanes x word) /clock cycle • Many Vector Procs. use banks (vs. simple interleaving): 1) support multiple loads/stores per cycle => multiple banks & address banks independently 2) support non-sequential accesses (see soon) • Note: No. memory banks > memory latency to avoid stalls • m banks => m words per memory lantecy l clocks • if m < l, then gap in memory pipeline: clock: 0 … l l+1 l+2 … l+m- 1 l+m … 2 l word: -- … 0 1 2 … m-1 -- … m • may have 1024 banks in SRAM**Vector Memory Requirements Example**• The Cray T90 has a CPU clock cycle of 2.167 ns and in its largest configuration (Cray T932) has 32 processors each capable of generating four loads and two stores per CPU clock cycle. • The CPU clock cycle is 2.167 ns, while the cycle time of the SRAMs used in the memory system is 15 ns. • Calculate the minimum number of memory banks required to allow all CPUs to run at full memory bandwidth. • Answer: • The maximum number of memory references each cycle is 192 (32 CPUs times 6 references per CPU). • Each SRAM bank is busy for 15/2.167 = 6.92 clock cycles, which we round up to 7 CPU clock cycles. Therefore we require a minimum of 192 × 7 = 1344 memory banks! • The Cray T932 actually has 1024 memory banks, and so the early models could not sustain full bandwidth to all CPUs simultaneously. A subsequent memory upgrade replaced the 15 ns asynchronous SRAMs with pipelined synchronous SRAMs that more than halved the memory cycle time, thereby providing sufficient bandwidth.**Vector Memory Access Example**• Suppose we want to fetch a vector of 64 elements starting at byte address 136, and a memory access takes 6 clocks. How many memory banks must we have to support one fetch per clock cycle? With what addresses are the banks accessed? • When will the various elements arrive at the CPU? • Answer • Six clocks per access require at least six banks, but because we want the number of banks to be a power of two, we choose to have eight banks as shown on next slide**Vector Length**• What to do when vector length is not exactly 64? • vector-length register (VLR) controls the length of any vector operation, including a vector load or store. (cannot be > the length of vector registers) do 10 i = 1, n 10 Y(i) = a * X(i) + Y(i) • Don't know n until runtime! n > Max. Vector Length (MVL)?**Strip Mining**• Suppose Vector Length > Max. Vector Length (MVL)? • Strip mining: generation of code such that each vector operation is done for a size Š to the MVL • 1st loop do short piece (n mod MVL), reset VL = MVL low = 1 VL = (n mod MVL) /*find the odd size piece*/ do 1 j = 0,(n / MVL) /*outer loop*/ do 10 i = low,low+VL-1 /*runs for length VL*/ Y(i) = a*X(i) + Y(i) /*main operation*/10 continue low = low+VL /*start of next vector*/ VL = MVL /*reset the length to max*/1 continue Time for loop:**Strip Mining Example**• What is the execution time on VMIPS for the vector operation A = B × s, where s is a scalar and the length of the vectors A and B is 200 (MVL supported =64)? Answer • Assume the addresses of A and B are initially in Ra and Rb, s is in Fs, and recall that for MIPS (and VMIPS) R0 always holds 0. • Since (200 mod 64) = 8, the first iteration of the strip-mined loop will execute for a vector length of 8 elements, and the following iterations will execute for a vector length of 64 elements. • The starting byte addresses of the next segment of each vector is eight times the vector length. Since the vector length is either 8 or 64, we increment the address registers by 8 × 8 = 64 after the first segment and 8 × 64 = 512 for later segments. • The total number of bytes in the vector is 8 × 200 = 1600, and we test for completion by comparing the address of the next vector segment to the initial address plus 1600. • Here is the actual code follows:**Strip Mining Example**The total execution time per element and the total overhead time per element versus the vector length for the strip mining example MVL supported = 64**Vector Stride**• Suppose adjacent elements not sequential in memory do 10 i = 1,100 do 10 j = 1,100 A(i,j) = 0.0 do 10 k = 1,100 10 A(i,j) = A(i,j)+B(i,k)*C(k,j) • Either B or C accesses not adjacent (800 bytes between) • stride: distance separating elements that are to be merged into a single vector (caches do unit stride) => LVWS (load vector with stride) instruction => SVWS (store vector with stride) instruction • Strides => can cause bank conflicts and a stall will occur if:**Vector Stride Memory Access Example**• Suppose we have 8 memory banks with a bank busy time of 6 clocks and a total memory latency of 12 cycles. How long will it take to complete a 64-element vector load with a stride of 1? With a stride of 32? Answer • Since the number of banks is larger than the bank busy time, for a stride of 1, the load will take 12 + 64 = 76 clock cycles, or 1.2 clocks per element. • The worst possible stride is a value that is a multiple of the number of memory banks, as in this case with a stride of 32 and 8 memory banks. • Every access to memory (after the first one) will collide with the previous access and will have to wait for the 6-clock-cycle bank busy time. • The total time will be 12 + 1 + 6 * 63 = 391 clock cycles, or 6.1 clocks per element.**Compiler Vectorization on Cray XMP**• Benchmark %FP %FP in vector • ADM 23% 68% • DYFESM 26% 95% • FLO52 41% 100% • MDG 28% 27% • MG3D 31% 86% • OCEAN 28% 58% • QCD 14% 1% • SPICE 16% 7% (1% overall) • TRACK 9% 23% • TRFD 22% 10%**Vector Chaining**• Suppose: MULV.D V1,V2,V3 ADDV.D V4,V1,V5 ; separate convoys? • chaining: vector register (V1) is not treated as a single entity but as a group of individual registers, then pipeline forwarding can work on individual elements of a vector • Flexible chaining: allow vector to chain to any other active vector operation => more read/write ports • As long as enough HW is available , increases convoy size • The above sequence is treated as a single convoy and the total running time becomes: Vector length + Start-up timeADDV + Start-up timeMULV**Vector Chaining Example**• Timings for a sequence of dependent vector operations MULV.D V1,V2,V3 ADDV.D V4,V1,V5 both unchained and chained.**Example Chained Execution of Vector Code**Vector Multiply Pipeline Vector Adder Pipeline Vector Memory Pipeline Scalar 8 lanes, vector length 32, chaining**Vector Conditional Execution**• Suppose: do 100 i = 1, 64 if (A(i) .ne. 0) then A(i) = A(i) – B(i) endif 100 continue • vector-mask controltakes a Boolean vector: when vector-mask (VM) registeris loaded from vector test, vector instructions operate only on vector elements whose corresponding entries in the vector-mask register are 1. • Still requires clock even if result not stored; if still performs operation, what about divide by 0?**Vector operations: Gather, Scatter**• Suppose: do 100 i = 1,n 100 A(K(i)) = A(K(i)) + C(M(i)) • gather (LVI) operation takes an index vectorand fetches the vector whose elements are at the addresses given by adding a base address to the offsets given in the index vector => a nonsparse vector in a vector register • After these elements are operated on in dense form, the sparse vector can be stored in expanded form by a scatter store (SVI), using the same index vector • Can't be done by compiler since can't know Ki elements distinct, no dependencies; by compiler directive • Use CVI to create index 0, 1xm, 2xm, ..., 63xm

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