Eng. Mohammed Timraz Electronics & Communication Engineer

1. University of Palestine Faculty of Engineering and Urban planning Software Engineering Department Digital Logic Design ESGD2201 Lecture 12 Function of Combinational Logic. Eng. Mohammed Timraz Electronics & Communication Engineer Saturday, 21th November 2009

2. Agenda Function of Combinational Logic. 1. Basic Adders. 2. Parallel Binary Adders. 3. Comparators. 4. Decoders. 5. Encoders. 6. Code Converters. 7. Multiplexers. 8. Demultiplexers.

3. Function of Combinational Logic. 2. Parallel Binary Adders: A single full-adder is capable of adding two 1-bit numbers and an input carry. To add binary numbers with more than one bit, additional full-adders must be used.

4. Function of Combinational Logic. 2. Parallel Binary Adders: When one binary number is added to another, each column generates a sum bit and a I or 0 carry bit to the next column to the left, as illustrated here with 2-bit numbers.

5. Function of Combinational Logic. 2. Parallel Binary Adders: To implement the addition of binary numbers, a full-adder is required for each bit in the numbers. So for 2-bit numbers, two adders are needed; for 4-bit numbers, four adders are used; and so on. The carry output of each adder is connected to the carry input of the next higher-order adder, as shown in the following Figure for a 2-bit adder.

6. Function of Combinational Logic. 2. Parallel Binary Adders: Block diagram of a basic 2-bit parallel adder.

7. Function of Combinational Logic. 2. Parallel Binary Adders: Block diagram of a basic 2-bit parallel adder. Notice that either a half- adder can be used for the least significant position or the carry input of a full-adder can be made 0 (grounded) because there is no carry input to the least significant bit position.

8. Function of Combinational Logic. 2. Parallel Binary Adders: Example 1: Verify that the 2-bit parallel adder in the following Figure properly performs the following addition

9. Function of Combinational Logic. 2. Parallel Binary Adders: Four-Bit Parallel Adders: A basic 4-bit parallel adder is implemented with four full-adders as shown in the following Figure, The LSBs (A1 and B1) in each number being added go into the right-most full-adder; The higher-order bits are applied as shown to the successively higher-order adders, with the MSBs (A4 and B4) in each number being applied to the leftmost full-adder. The carry output of each adder is connected to the carry input of the next higher-order adder as indicated. These are called internal carries.

10. Function of Combinational Logic. 2. Parallel Binary Adders: Four-Bit Parallel Adders: (a) Block diagram

11. Function of Combinational Logic. 2. Parallel Binary Adders: Four-Bit Parallel Adders: In keeping with most manufacturers’ data sheets, the input labeled C0 is the input carry to the least significant bit adder; C4, in the case of four bits, is the output carry of the most significant bit adder; and (LSB) through (MSB) are the sum outputs. (b) Logic symbol

12. Function of Combinational Logic. 2. Parallel Binary Adders: The truth table for a Four-Bit Parallel Adders: NOTE: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs ∑1 and ∑2, andvalue of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs ∑3, ∑4 and C4.

13. Function of Combinational Logic. 2. Parallel Binary Adders: The truth table for a Four-Bit Parallel Adders:

14. Function of Combinational Logic. 2. Parallel Binary Adders: Example 2: Use the 4-bit parallel adder truth table to find the sum and output carry for the addition of the following two 4-bit numbers if the input carry is 0: A4A3A2A1 = 1100 and B4B3B2B1 = 1100 Solution: For A1 = 0, B1 = 0, A2 = 0, B2 = 0, and C0=0, the first row in the output columns for C0=0 in the truth table shows that ∑1=0, ∑2=0, and C2 = 0. Next, for A3 = 1, B3 = 1, A4 = 1, B4 = 1, and C2=0, the last row in the output columns for C2=0 in the table shows that ∑3=0, ∑4=1, and C4 = 1. The following addition agrees with the table:

15. Function of Combinational Logic. 2. Parallel Binary Adders: The 74LS83A and 74LS283 MSI (medium-scale integrated) Adders: • Examples of 4-hit parallel adders that are available as medium-scale integrated (MSI) circuits are the 74LS83A and the 74LS283 low-power Schottky TTL devices. • These devices are also available in other logic families such as standard EEL (7483A and 74283) and CMOS (74HC283). • The 74LS83A and the 74LS283 are functionally identical to each other but not pin compatible; that is, the pin numbers for the inputs and outputs are different due to different power and ground pin connections. • For the 74LS83A, Vcc is pin 5 and ground is pin 12 on the 16-pin package. • For the 74LS283, Vcc is pin 16 and ground is pin 8, which is a more standard configuration. • Logic symbols for both of these devices are shown, with pin numbers in parentheses, in the following Figure.

16. Function of Combinational Logic. 2. Parallel Binary Adders: The 74LS83A and 74LS283 MSI (medium-scale integrated) Adders: MSI 4-bit parallel adders.

17. A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 C0 C5 ∑4 ∑5 ∑3 ∑2 ∑1 Function of Combinational Logic. 2. Parallel Binary Adders: Example 2: Construct a parallel full adder system to add 2 numbers with 5 bits. Solution:

18. Function of Combinational Logic. 3. Cascading Adders: The 4-bit parallel adder can be expanded to handle the addition of two 8-bit numbers by using two 4-bit adders and connecting the carry input of the low-order adder (C0) to ground because there is no carry into the least significant bit position and by connecting the carry output of the low-order adder to the carry input of the high-order adder as shown in the following Figure (a). (a) cascading of 4-bit adders to form an 8-bit adder

19. Function of Combinational Logic. 3. Cascading Adders: Similarly, four 4-bit adders can he cascaded to handle two 16-bit numbers as shown in the following Figure (b). Notice that the output carry is designated C16 because it is generated from the sixteenth bit position. (b) cascading of 4-bit adders to form a 16-bit adder

20. Function of Combinational Logic. 3. Cascading Adders: Example 3: Show how two 74LS83A adders can be connected to form an 8-bit parallel adder. Show output bits for the following 8-bit input numbers: and Solution: Two 74LS83A 4-bit parallel adders are used to implement the 8-bit adder. The only connection between the two 74LS83As is the carry output (pin 14) of the low-order adder to the carry input (pin 13) of the high-order adder, as shown in the following Figure. Pin 13 of the low-order adder is grounded (no carry input).

21. Two 74LS83A adders connected as an 8-bit parallel adder (pin numbers are in parentheses).

22. Function of Combinational Logic. 2. Parallel Binary Adders: An Application • An example of full-adder and parallel adder application is a simple voting system that can be used to simultaneously provide the number of "yes" votes and the number of "no" votes. • This type of system can be used where a group of people are assembled and there is a need for immediately determining opinions (for or against), making decisions, or voting on certain issues or other matters.

23. A voting system using full-adders and parallel binary adders.