High Speed Digital Design Project

1. High Speed Digital Design Project SpaceWire Router Part A Final Presentation By: AsafBercovich & Oren Cohen Advisor: MonyOrbach Semester: Winter 2007/2008 2-Semester Project Date: October 2008

2. Project Goal • Designing a SpaceWireSwitch Core (Router) compatible to ECSS-E-50-12A Standard. • The design will be coded and simulated using Xilinx development enviroment and implemented onto a Xilinx VirtexII-Pro FPGA.

3. System Topology Router

4. System Topology • Full duplex • Low latency • Point-to-point • Wormhole Routing • Asynchronous communication • Automatic failover • 400 Mb/s of Traffic Total Router PORT

5. D1117 SpaceWire Port Architecture Tx Clock TX Clock Write Ready Dout Read Ready FIFO Transmitter Sout TX DATA / Control Reset HOST OUTER WORLD Port Controller Link Start Link Ready State Machine Sys Clock Read Din Ready Write FIFO Ready Receiver Sin RX CLOCK RX DATA / Control Layer 2 (Character Level) Network Port

6. Port Transmitter“The Factory” TX DATA Shift Register Control Signals TX Clock Controller SpaceWire Character Logic Logic Logic Dout DS Encoder Sout

7. D1117 SpaceWire Port Architecture Tx Clock Write Ready Dout Read Ready FIFO Transmitter Sout TX DATA / Control Reset HOST OUTER WORLD Port Controller Link Start Link Ready State Machine Sys Clock Read Din Ready Write FIFO Ready Receiver Sin RX CLOCK RX DATA / Control Layer 2 (Character Level) Network Port

8. Port Receiver RX Clock Recovery Error Reporting RX_DATA to FIFO MEM Din Shift Register Logic Logic Rx Clock Din Sin

9. D1117 SpaceWire Port Architecture Tx Clock Write Ready Dout Read Ready FIFO Transmitter Sout TX DATA / Control Reset HOST OUTER WORLD Port Controller Link Start Link Ready State Machine Sys Clock Read Din Ready Write FIFO Ready Receiver Sin RX CLOCK RX DATA / Control Layer 2 (Character Level) Network Port

10. Internal Signals Transmitter RESET Send NULLs Send FCTs Send N-Chars Send Time-Codes Port Controller (State Machine) GotFCT Got Time-Code GotN-Char GotNULL CreditError RX_Err RESET Receiver

11. Port Main Control – Overview Run Send All Enable Rx Error Reset Reset Tx Reset Rx Error Wait Reset Tx Enable Rx ? [Link Disabled] After 6.4 ɥs Rx Err OR Rx Err OR Credit Error Got Fct Got NChar After 12.8 ɥs Got Fct Got NChar Got Fct Rx Err OR Rx Err OR After 12.8 ɥs After 12.8 ɥs Rx Err OR Got NChar Got Fct Got NChar Connecting Send Fct/Null Enable Rx Started Send Null Enable Rx Ready Reset Tx Enable Rx Got Null [ Link Start ]

12. Port Main Control - Problem Run Send All Enable Rx Error Reset Reset Tx Reset Rx Error Wait Reset Tx Enable Rx [Link Disabled] After 6.4 ɥs Rx Err OR Rx Err OR Credit Error Got FCT Got NChar After 12.8 ɥs Got FCT Got NChar Got FCT Rx Err OR Rx Err OR After 12.8 ɥs After 12.8 ɥs Rx Err OR Got NChar Got FCT Got NChar Connecting Send Fct/Null Enable Rx Started Send Null Enable Rx Ready Reset Tx Enable Rx Got Null [ Link Start ]

13. Port Main Control - Resolution Run Send All Enable Rx Error Reset Reset Tx Reset Rx Error Wait Reset Tx Enable Rx [Link Disabled] After 6.4 ɥs Rx Err OR Rx Err OR Credit Error Got FCT Got NChar After 12.8 ɥs Got FCT Got NChar Got FCT Rx Err OR Rx Err OR After 12.8 ɥs After 12.8 ɥs Rx Err OR Got NChar Got FCT Got NChar Connecting Send Fct/Null Enable Rx Started Send Null Enable Rx Ready Reset Tx Enable Rx Got Null [ Link Start ]

14. D1117 SpaceWire Port LVDS Interface Tx Clock LVDS Drivers Dout+ Write Ready Dout Dout- Read Ready FIFO Transmitter Sout TX DATA / Control Sout+ Reset HOST OUTER WORLD Port Controller Sout- Link Start Link Ready State Machine Sys Clock Din+ Read Din- Din Ready Write FIFO Ready Receiver Sin RX CLOCK Sin+ RX DATA / Control Sin- Layer 2 (Character Level) Network Port

15. SpaceWire Interface • SpaceWire connectors are driven by Low Voltage Differential Signaling (LVDS) system (2.5 Volts). • Signal conversion to LVDS is required. Inner shield Sin+ Din+ Dout- Sout- Sin- Din- Dout+ Sout+ SpaceWirePinOut

16. Testing The Core • Programming GR-RASTA Board (based on VirtexII) with the SpaceWire Port’s Core. • Connecting the RASTA-Board SPW interface to Gaisler’s GRESB SpaceWire Bridge. • Verifying correctness of our core by sending megabytes of files between our port and the GRESB bridge and vice versa. • monitoring iMPACT

17. Project MilestonesFocus on the Router • Examination of several switching architectures. • Designing the network configuration and layout. • Implementation of the router core and supporting logics. • Validating correctness of the router.