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Cadence’s Solution for High-Speed Design

Cadence’s Solution for High-Speed Design. Agenda. What is High-Speed Design? Ideal High-Speed Design Process Introduction to SPECCTRAQuest Power Integrity SPECCTRAQuest Demonstration. The Day of “High-Speed” Has Come.

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Cadence’s Solution for High-Speed Design

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  1. Cadence’s Solution for High-Speed Design

  2. Agenda • What is High-Speed Design? • Ideal High-Speed Design Process • Introduction to SPECCTRAQuest Power Integrity • SPECCTRAQuest Demonstration

  3. The Day of “High-Speed” Has Come “Pc-board designers, meanwhile, were retooling in 1999 for high-speed design. Signal integrity, once confined to high-end boards, has become everybody’s problem…” Richard Goering, commenting on why the PCB layout market grew 20%while the IC layout market shrunk 30%, in EETimes 4/10/2000 page 70

  4. Welcome Networking! HammerheadNetworks

  5. Agenda NOW • What is High-Speed Design? • Ideal High-Speed Design Process • SPECCTRAQuest Demonstration • Introduction to SPECCTRAQuest Power Integrity

  6. What is “High-Speed” ? “High-Speed” isn’t relatedto frequency, it’s a functionof rise times Over 50 MHzis “High-Speed” A net is “High-Speed” when itsround-trip delay is greaterthan twice its edge-speed A signal is “High-Speed”when it is faster thananything you’ve designed before “High-Speed” occurs whenskin effect and dielectricloss effects become important Huh?

  7. Question: Which is a “High-Speed” Problem?

  8. Answer: They BOTH Are !!

  9. Definition of High-Speed A net can be considered ‘High-Speed’ when you have to do something other than simply connect it.

  10. High-Speed Design Involves 2 Things • Nets that are understood, and must be constrained • Nets that must be analyzed to be understood, and then constrained

  11. Nets that are understood, and must be constrained • Nets that must be analyzed to be understood, and then constrained SDRAM DIMM Layout MODELS Datasheets Front-side Bus Simulation

  12. Most Tools Force You to Choose GreatSimulator! GreatLayoutSystem! Analyze Constrain Hmm...

  13. Analyze &Constrain But for High-Speed You Need BOTH All in ONE integrated & interactive environment ! Let’s Go!

  14. Post Route Analysis Verification Verification SPECCTRAQuest: Integrated Constraint & Analysis Model Development & Verification Pre-Route Sol’n-Space Analysis SPECCTRAQuest helps you manage the process of High-Speed PCB development through both Simulation Analysis & Constraint-Driven Layout tasks A Complete Solution! Analyze Topology Entry & Floorplanning Constraint Driven Layout Constrain

  15. HIGH-SPEED Electrical Model Creation rules/ criticals/ placement / ACs Derive Constraints “IP” Library Re-use Topology Files Topology Files Topology Files constraints Post-Route Analysis OK? no yes Expanding Existing Process SCHEMATIC LAYOUT Schematic Model Creation Physical Model Creation Schematic Creation Outline/ Floorplan/ Room Def/ netlist PCB Routing Back- Annotate SI Clean Route To Final Verification

  16. Agenda • What is High-Speed Design? • Ideal High-Speed Design Process • SPECCTRAQuest Demonstration • Introduction to SPECCTRAQuest Power Integrity NOW

  17. Post Route Analysis Verification Verification Ideal High-Speed Design Flow Model Development & Verification Development Process Flow Model Development & Verification Pre-Route Sol’n-Space Analysis Analyze Topology Entry & Floorplanning Constraint Driven Layout Constrain

  18. IBIS SPICEModels Version 2.1 Version 3.2 Need Flexible Device Modeling Language (DML) CadenceDML Package,Transmission Line,Connector, Cable Models • Today’s models come in many styles and formats • Cadence DML can model all formats AND advanced behaviors(for example, Merced / Itanium) EBDModels QuadModels can’t do “M” element today

  19. Post Route Analysis Verification Verification Ideal High-Speed Design Flow Pre-Route Sol’n-Space Analysis Development Process Flow Model Development & Verification Pre-Route Sol’n-Space Analysis Analyze Topology Entry & Floorplanning Constraint Driven Layout Constrain

  20. Pre-Route Solution Space Analysis • Exhaustive “pre-layout” analysis of manufacturing and design variances • Used to define topologies, routing rules and termination strategies • Crosstalk and data pattern dependencies may be taken into consideration • Swept-parameter analysis is used extensively to cover all combinations of conditions • Need flexibility to define any kind of simulation and any kind of measurement criteria

  21. Topology Templates Derive and Save “Solution Space” Constrain Output of pre-layout process is an electronic constraint file that can be used to guide the layout process Analyze

  22. Post Route Analysis Verification Verification Ideal High-Speed Design Flow Development Process Flow Model Development & Verification Pre-Route Sol’n-Space Analysis Analyze Topology Entry & Floorplanning Topology Entry & Floorplanning Constraint Driven Layout Constrain

  23. High-Speed PCB Design Now Requires Both Electronic Inputs to Floorplanning & Routing

  24. Topology Templates Topology Entry and Floorplanning • Design rules derived from solution space analysis guide the placement process • Constraint Manager spreadsheets plays a key role in guiding / evaluating component placement • Margin columns show difference between constraint and design value • Fast feedback • Color-coded status

  25. Post Route Analysis Verification Verification Ideal High-Speed Design Flow Development Process Flow Model Development & Verification Pre-Route Sol’n-Space Analysis Analyze Constraint Driven Layout Topology Entry & Floorplanning Constraint Driven Layout Constrain

  26. Constraint Management Today GUI GUI GUI GUI Exploration Capture Floorplanning Layout HyperLynx Design ? ? ? VeriBest ePlanner Architect ePlanner/QUAD Board Station ICX SPICE ViewDraw PADS Constraints Constraints Constraints Constraints Constraint Manager SPECCTRAQuest Exploration ConceptHDL Capture SPECCTRAQuest Floorplanning Allegro/APD Layout

  27. PSD 14.0 Constraint Manager • Common, powerful environment for constraint entry / editing / management and verification • Single mechanism for managing constraints throughout the design process

  28. Constraint Manager – Key Features • Spreadsheet-based graphical interface • No cryptic formats or cumbersome updating • Provides unsurpassed Integration across the entire design flow • Consistent Front to Back solution • No messy translations with static constraint data • Directly integrated with schematic and PCB databases • Analysis engines can update spreadsheet data interactively

  29. Constraint Manager – Hierarchy • Allows constraints to be managed hierarchically • Groups of rules are maintained as Electrical Constraint Sets (ECSets) • Provides single point for updating rules or assigning to nets • ECSets can be applied to groups of nets (buses) with individual overrides

  30. Termination RIMM Chipset Constraint Manager – Systems • Support for system level constraints • Constraints can span PCB boundaries

  31. Topology Templates Constraint Driven Layout Guides: • Floorplanning • Hand Layout • Auto-Route

  32. Constraint Driven Layout • Design rule violations during interactive routing are identified in real-time • Autorouter follows design rules - powerful integration with SPECCTRA! • Because solution space analysis has defined a set of conditions under which the nets are known to work, chance of first-pass success is high. • Nets can be ripped up and rerouted, as long as they still adhere to the design rules

  33. Post Route Analysis Verification Verification Ideal High-Speed Design Flow Post Route Analysis Verification Development Process Flow Model Development & Verification Pre-Route Sol’n-Space Analysis Analyze Verification Topology Entry & Floorplanning Constraint Driven Layout Constrain

  34. Agenda • What is High-Speed Design? • Ideal High-Speed Design Process • Introduction to SPECCTRAQuest Power Integrity • SPECCTRAQuest Demonstration NOW

  35. SPECCTRAQuest Power Integrity Module The Future of Power Delivery System Design

  36. SPECCTRAQuest Power Integrity • Innovative technology developed and proven by Sun Microsystems, now commercialized by Cadence Design Systems, Inc. to address Power Delivery issues in high-speed PCB System Designs. • A design tool / methodology used to design and optimize the frequency-dependent characteristics of Power Delivery Systems in high-speed system designs • An integrated solution to allow many quick iterations of “change-simulate-analyze”

  37. Power Delivery Requirements Trend • Power dissipation and longer battery life fueling decreasing chip power supply voltages • Maximum allowable supply ripple decreases accordingly • SoC, SiP fueling trend towards devices with large number of devices • The instantaneous switching current required is enormous • The maximum acceptable power supply ripple voltage determines the target impedance which must be maintained across the PCB • Maximum supply impedance must be less than 0.002 Ohms

  38. Power Delivery System Design Challenges • Power supply droop • Alters system timing and can cause Setup failures • Can cause sampling errors that results in a system crash • Unreliable power delivery system design can cause increased common-mode EMI preventing product shipment due to compliance problems • Power delivery system impedance is frequency-dependent • Must be controlled for all frequency range of all transient currents Increases Development Costs and Time to Market is LOST!

  39. Power Delivery System Design -How it is done today • Standalone analysis tools • Design data translation is left up to the user • Changes to the design resulting from simulation is manual • Use Time Domain simulation • Power delivery system impedance is frequency-dependent! • With only time domain simulation, it is like searching for needle in a haystack • Over design - add more de-coupling capacitors than necessary • Expensive solution that may not work

  40. The Cadence approach • Allow users to determine the needs of the power delivery system • Target impedance • Decoupling capacitor requirements • Provide frequency domain analysis to find problem areas • Provide an integrated PCB design editor to optimize capacitor placement Develop reliable power delivery system while shortening design cycle time

  41. SPECCTRAQuest Power Integrity -Software Components • Frequency-domain analysis engine • Integrated PCB editor that includes Decoupling capacitor placement environment • Impedance requirements calculator • Decoupling requirements wizard • High speed capacitor library / library editor

  42. Isolating Decoupling Problem Areas

  43. Device Placement – Decoupling Capacitors • Capacitors can be selected from the decoupling “menu” and placed into the design • The effective decoupling radius is automatically displayed as the capacitor is positioned • Designers continue to adjust capacitor selection & placement until performance of the PDS is acceptable Allows many “change-simulate-analyze” cycles in a short time

  44. Release • Available with PSD release version 14.1 • Scheduled for late Q2, 2001 • First release available on Sun Solaris (7 / 8) only • Other platforms to follow with next major release

  45. SPECCTRAQuest Power Integrity - Summary • Innovative technology developed and proven by Sun Microsystems, commercialized by Cadence • Combined toolset and methodology for the design and analysis of high performance power delivery systems • Offered as an option to SPECCTRAQuest, integrated with Allegro • Part of Cadence’s complete family of Signal Integrity / Power Delivery / EMI solutions Shortens Development Cycle and Time to Market!

  46. Agenda • What is High-Speed Design? • Ideal High-Speed Design Process • Introduction to SPECCTRAQuest Power Integrity • SPECCTRAQuest Demonstration NOW

  47. SPECCTRAQuest Demonstration (please ask questions as we proceed!)

  48. What You Will See • Intel PIII / BX Reference Design • 100 MHz Front-Side Bus • Analysis & Constraint Process • Board Level • Electrical Level • Constraint Integration • Advanced Processing

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