High Speed Digital Design Project

High Speed Digital Design Project SpaceWire Router Part B - Final Presentation Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date: Januar 2010

Project Goal • Designing a SpaceWireSwitch Core (Router) compatible to ECSS-E-50-12A standard with the “Path Addressing” routing scheme. Project Results • D1117_SPWPort – SpaceWire Network Device • D1117_SPWRepeater – SpaceWire Network Repeater • D1117_SPWRouter – SpaceWire Router

System Topology SpaceWire Router

System Topology • Low latency • Point-to-point • Wormhole Routing • Asynchronous communication • Path Addressing • 100 Mb/s of Total Traffic. D1117_SPWRouter PORT

D1117 SpaceWire Port Architecture Tx Clock Write Ready Dout Read Ready FIFO Transmitter Sout TX DATA / Control Reset HOST OUTER WORLD Port Controller Link Start Link Ready State Machine Sys Clock Read Din Ready Write FIFO Ready Receiver Sin RX CLOCK RX DATA / Control Layer 2 (Character Level) Network Port

System Topology • Low latency • Point-to-point • Wormhole Routing • Asynchronous communication • Path Addressing • 100 Mb/s of Total Traffic. D1117_SPWRouter PORT

SpaceWire Packet Format <DESTINATION><CARGO><END OF PACKET> SpaceWire Packet SpaceWire ‘Routing Switch’ A SpaceWire ‘Routing Switch’ shall transfer packets from the input port of the switch where the packet arrives, to a particular output port determined by the packet destination address.

Routing with Path-Addressing 4 3 2 Cargo EOP

Layer 2 Repeater RX_EMPTY TX_FULL D1117_SPWRepeater TX_WRITE READ_EN Write Interface Read Interface RX_CONTROL TX_CONTROL ENABLE SPW Port-1 SPW Port-0 RX_DATA TX_DATA SpaceWire Connection Broker SpaceWire signals SpaceWire signals

Router Architecture SYSTEM_CLOCK Source Address Register REGISTERED_SOURCE_ADDR TX_FULL TX_FULL RX_EMPTY RX_EMPTY RX_EMPTY TX_FULL TX_FULL REGISTERED_DEST_ADDR TX_WRITE TX_WRITE` TX_WRITE TX_WRITE READ_EN READ_EN READ_EN Read Interface Write Interface Read Interface Write Interface Write Interface Read Interface TX_CONTROL TX_CONTROL RX_CONTROL RX_CONTROL RX_CONTROL TX_CONTROL TX_CONTROL SPW Port-1 SPW Port-2 SPW Port-1 SPW Port-0 SPW Port-0 SPW Port-2 Destination Address Register TX_DATA TX_DATA RX_DATA RX_DATA RX_DATA TX_DATA TX_DATA RX_EMPTY SpaceWire Connection Broker READ_EN Write Interface Read Interface Write Interface SpaceWireMux Read Interface SpaceWireMux RX_CONTROL RX_DATA EN_SOURCE_ADDR_REGISTER EN_DEST_ADDR_REGISTER EN_PACKET_DELIVERY HEADER_DELETION Packet Detection Unit SpaceWire Router Control EOP Detection Unit EOP_DETECTED PACKET_DETECTED

Router Controller “CONFIGURE DESTINATION ADDRESS” “CONFIGURE SOURCE ADDRESS” “IDLE” “RESET” “WAIT FOR EOP/EEP” SPW PORT RESET = 1 All other controller output signals are zero. All controller output signals are zero. PACKET_DETECTED=1 EOP_DETECTED=1 EN_PACKET_DELIVERY = 1 All other controller output signals are zero. EN_DEST_ADDR_REGISTER = 1 HEADER_DELETION = 1 All other controller output signals are zero. EN_SRC_ADDR_REGISTER = 1 All other controller output signals are zero.

Hardware in test • GR-RASTA running D1117_SPWRouteras SpaceWire router. • Gaisler GRESB – Gaisler Ethernet Bridge.(To be explained.) • 3 PCs as SpacWire stations connected to one D1117 SpaceWire Router. Together they form a SpaceWire network based on ‘Path Addressing’ routing.

Software in test • TCP Test Tool 2.3 Freeware.www.SimpleComTools.com

Main Test Topology PC-0 OS: Windows PC-1 OS: Windows PC-2 OS: Windows Logic Link SPW-0 SPW-1 SPW-2 Core : D1117 SpaceWire RouterFPGA : GR-RASTA

Main Test Topology PC-0 OS: Windows PC-1 OS: Windows PC-2 OS: Windows Ethernet Ethernet GaislerSpaceWire Ethernet Bridge SPW-0 SPW-1 SPW-2 Core : D1117 SpaceWire RouterFPGA : GR-RASTA SPW-0 SPW-1 SPW-2 SpaceWire

SpaceWire Ethernet Bridge Ethernet GaislerSpaceWire Ethernet Bridge SPW-0 SPW-1 SPW-2

PC-0 The TCP Listening Socket on the GRESB. 2000 TCP port corresponds for transmission on SpaceWire port 0. IP Address of GRESB on the IP network. TCP Message Headerspecifying transmission of a SpaceWire packet the size of 6 bytes. Cargo Path Address Destination Address Send button for dispatching the TCP Message to GRESB

PC-1 Encapsulated SpaceWire Packet TCP Message Headerspecifying reception of a SpaceWire packet the size of 5 bytes.

Test Miscellaneous • “2 Routers Topology” was tested in addition to the “Main Topology” to simulate complex routes in a SpaceWire network with more then one router. • D1117_SPWRouter delivered successfully thousands of SpaceWire packets originated in PCs, to correct destinations which are PCs as well on the same SpaceWire network.

Further Possibilities • The router can be redesigned for multiple connections ‘routing matrix’. Currently the datapath of the router can only support one simultaneous connection from port to port. • The router can be extended to support more SpaceWire routing schemes. (Not just Path Addressing + Header Deletion). • The router can be redesigned for higher data rate ~200Mhz on the XC2v6000 FPGA using pipeline design. • Writing a software Device Driver for windows to virtually make GRESB a SpaceWire network connection on a PC. It can be done by implementing a Device Driver which exposes an Ethernet Device abstraction towards Windows and on the other side, coding SpaceWire packets on GRESB. Such a Device Driver actually solves the problem of “Ethernet over SpaceWire” for PC.

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High Speed Digital Design Project