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912.001 Layout Planning of Mixed-Signal Integrated Circuits Chung-Kuan Cheng / Andrew B. Kahng UC San Diego CSE Departm PowerPoint Presentation
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912.001 Layout Planning of Mixed-Signal Integrated Circuits Chung-Kuan Cheng / Andrew B. Kahng UC San Diego CSE Department. Planning. Goals Timing Power Feasibility. Elements Blocks Power/Ground Clocks Buses. Resources Silicon Routing layers. Mixed-Signal Planning. Goals Timing

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slide1

912.001 Layout Planning of Mixed-Signal Integrated CircuitsChung-Kuan Cheng / Andrew B. KahngUC San Diego CSE Department

planning
Planning

Goals

Timing

Power

Feasibility

Elements

Blocks

Power/Ground

Clocks

Buses

Resources

Silicon

Routing layers

mixed signal planning
Mixed-Signal Planning

Goals

Timing

Power

Feasibility

Elements

Blocks

Power/Ground

Clocks

Buses

Resources

Silicon

Routing layers

Unified and constrained: (1) polygon- and die-level optimizations; (2) device / interconnect embedding; (3) performance analysis and layout synthesis

mixed signal planning scope
Mixed-Signal Planning Scope

System

Geometry, Wires

Architecture

RF, Analog

Digital

Floorplan

Logic

Feasibility, Performance

Layout

initial project activities
Initial Project Activities
  • Useful Background
  • Interconnect synthesis (P/G, clock, signal topology) and RLC analysis (book,glossary)
  • Multilevel optimizers since 1995: partitioning (MLPart), placement (Capo, CapoT)
  • Primal-dual optimization frameworks
  • Floorplan representations and optimizations: O-tree, corner block list, … + compaction
  • M/S Context
  • Circuit/System types
  • Constraint types
  • Figures of merit
  • Design/layout best practices

M/S Planning Capability

Develop

  • Layout Representation
  • Devices, interconnects both first-class citizens
  • System-level interconnect synthesis (e.g., arch / “cells”)
  • Hybridization of topological, spatial representations
  • Digital + A/MS Integration
  • Power
  • Isolation
  • Technology (device and interconnect variability, heterogeneous integration)

Leverage

  • Students, Faculty
  • Bo Yao (PhD 2005), Mingyuan Li (PhD 2006)
  • C.-K. Cheng, Andrew Kahng

Use Model

  • Constraint-Dominated Optimization
  • Scalable, high-quality
  • Focus on mixed-mode embedding, “primal-dual” opt

Understand

mixed mode embedding
Mixed-Mode Embedding
  • Traditional blocks
  • Traditional cells
  • Mixed-Mode (blocks + cells)
  • Mixed-Signal
    • RF, Analog, Digital Modules + Wires
slide8

Hierarchy Management/Reconciliation

“Layout Tree”

“Design Tree”

traditional context digital
Traditional Context: Digital

Control logic allowed to overlap because these are regions, not exact placements of hard cells.

Control

Datapath

High regularity of datapath logic

DP, repeaters, clock buffers, memory, BIST,…

classical floorplanning harmful tutorial slide ispd april 2000
“Classical Floorplanning Harmful” tutorial slide, ISPD April 2000

http://vlsicad.ucsd.edu/papers/slides/ispd00-cfh.ppt

cell placement
Cell Placement
  • (Commoditized)
  • Based on:
    • Multi-level clustering (RTL hierarchy-aware, HEM, PinHEM, HEC, Rent-based, etc. etc. etc. variants)
    • Hybrid of analytic and partitioning methods
    • Bundled with incremental STA, basic timing/SI-driven opts
  • Assume can leverage existing, foreseen technology
    • SPC, Cadence/Avant!/Mentor, Synopsys/Magma, …
    • Capo, CapoT, Dragon, Mongrel, Feng Shui (various LEF/DEF compatible open-source placers in MARCO GSRC Bookshelf)
o tree representation
O-Tree Representation
  • Representation = key issue
    • Cover all kinds of floorplans
    • Easy to manipulate
  • O-tree = good candidate
    • Covers both slicing and non-slicing
    • O(n) time to derive the floorplan
    • Handles various constraint types, e.g., symmetry
    • Tree structure  easy to represent interconnect channels
  • Current goal: Equal representation of both “modules” and interconnects
analog layout issues
Analog Layout Issues
  • Power, ground, guard ring design
  • Centering (thermal, process,…)
  • Matching issues
    • Area: manage relative impact
    • Distance: match environment effects
    • Shape, orientation: match process distortions
    • Symmetry: differential signaling
  • Constraints
    • Parasitics: diffusion parasitic C, R; inductance (high-freq); interconnect coupling)
    • Geometry: fixed locations, ARs/dimensions
  • Isolation
    • Substrate noise: distance, guard rings
    • Thermal variation: distance from hot spots
    • Power supply distribution
rf layout issues
RF Layout Issues
  • Power/Ground
  • EMI
  • Main goal = performance
  • RF design is wire-dominated
    • Precise wire topology, length
    • Planar layout
  • Cf. Aktuna/Rutenbar 1999
sensitivities and primal dual framework
Sensitivities and Primal-Dual Framework
  • Planning tools must understand sensitivities
    • Buffer insertion, gate sizing, replication
    • Wire sizing, shielding, signaling architecture
  • Primal:
    • Timing, routing completion, …
  • Dual:
    • Net cost, path cost, routing area cost, placement location cost, …
  • Experience with e.g., provably good primal-dual approximations for multi-commodity flow (ICCAD00, ASPDAC01, ASPDAC02)
floorplan representations
Floorplan Representations

Slicing Ordered Tree

Sequence Pair

Corner Block List

Twin Binary Tree

Ordered Tree

slicing floorplan

A

E

D

B

F

C

Slicing Floorplan

colors of adjacent

nodes differ

D

F

E

Slicing Ordered Tree

A

C

B

slide22

F

C

E

A

E

B

B

C

A

0

X

D

X

1

X

D

A

D

E

1

F

B

F

0

1

X

C

0

1

0

0

1

Twin Binary Trees

(1)=11001

(2)=00110

order(t1)=order(t2)=ABCDFE

slide23

B

C

A

B

C

D

A

D

F

E

E

F

O-Tree

SP1=(ABCDFE,FADEBC)

SP2=(ABCDFE,FADBEC)

CBL=(FADEBC,11101,0010100)

CBL90=(ABCDFE,00110,00101010)

relations between representations
Relations Between Representations

900

O-tree

T

SP

(s1,s2)

TBT

(t+,t-)

CBL

(S,L,T)

tree transform

sequence