1 / 6

Paper Report

Paper Report. On the Generation of Functional Test Programs for the Cache Replacement Logic. W. J. Perez H . Universidad del Valle Grupo de Bionanoelectrónica Cali , Colombia Universidad Pedagógica y Tecnológica de Colombia , Grupo Gira Sogamoso , Colombia

snow
Download Presentation

Paper Report

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Paper Report On the Generation of Functional Test Programs for the Cache Replacement Logic W. J. Perez H. Universidad del Valle Grupode Bionanoelectrónica Cali, Colombia Universidad Pedagógicay Tecnológicade Colombia, GrupoGiraSogamoso, Colombia D. Ravotto, E. Sanchez, M. Sonza Reorda, A. Tonda Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy 2009 Asian Test Symposium Presenter: Jyun-Yan Li

  2. What is the Problem • IC manufacturing cost most at test and validation processor • Not enough methodology to cope with all testing issue for cache • Cache testing approaches • Hardware based • Usually modifies initial design in order to support testing procedures • Algorithm based • March-like program test data cache • focusing on testing memory element not cache controller • Software-based Self-Test (SBST) depend on effective test program

  3. Related work SBST Data cache Processor Embedded processor [6] Direct mapped data cache [16] Data controller [8] Determine cache Hit or miss by access cycle which is counter Test cache memory module & control logic Divide & conquer for each processor components to generate test pattern A hybrid method for data & instruction controller [9] Determine cache Hit or miss by I-IP which observes response and generates error signal On the Generation of Functional Test Programs for the Cache Replacement Logic This paper:

  4. Proposal method • Build FSM of the replacement mechanism • Input I • n address stored in the n ways of cache set • Some address produce a cache miss for transfer new state • Output O • hit or miss • State S • Permutation of n way which way can be replaced • Generate a test sequence for testing replacement mechanism • Finding a tour to traverse every edge • generating the sequence of addresses to traverse all the transitions

  5. Experimental result • LEON2 processor with a 3-way data cache • Write through policy • Write no-allocate on a write miss • LRU replacement • Stuck at fault • Cache controller: 26148 • LRU: 11637

More Related