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Paper Report. Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors. Heon-Mo Koo Intel Corporation, 1900 Prairie City Road Folsom, CA 95630, USA Prabhat Mishra

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paper report

Paper Report

Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors

Heon-Mo Koo

Intel Corporation, 1900 Prairie City Road Folsom, CA 95630, USA

PrabhatMishra

Computer & Information Science & Engineering ,University of Florida, Gainesville, FL 32611, USA

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis

Presenter: Jyun-Yan Li

abstract
Abstract
  • Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biased-random test programs. Although directed tests require a smaller test set compared to random tests to achieve the same functional coverage goal, there is a lack of automated techniques for directed test generation. Furthermore, the number of directed tests can still be prohibitively large.
  • This paper presents a methodology for specification-based coverage analysis and test generation. The primary contribution of this paper is a compaction technique that can drastically reduce the required number of directed test programs to achieve a coverage goal. Our experimental results using a MIPS processor and an industrial processor (e500) demonstrate more than 90% reduction in number of directed tests without sacrificing the functional coverage goal.
what is the problem
What is the Problem

Random and biased-random test program generation is widely used

  • Simulation-based validation in the design cycle
  • Directed test generation has shorter tests in the same coverage

Directed test still large

  • Multiple pipeline interactions reaches the target functional
  • Test generation after compact
  • This paper present FSM directed test generation
related work
Related work

FSM model

[2, 20]

Complex FSM models, state explosion problem

Static Test compaction

Architecture Description Language (ADL)

[12]

Model checker

[10, 11]

Remove unreachable & redundant state

Abstraction FSM model

[3, 8, 13,15, 17]

Produce test program

Generated from the abstract FSM

Reduce unnecessary state

Define processor’s functionalities

Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors

This paper:

proposal method outline
Proposal method outline
  • FSM modeling of pipelined processor
  • Remove unreachable states
  • Remove illegal transitions
  • Remove redundancy state
  • Test generation
pipeline processor fsm model
Pipeline processor FSM model
  • Modeling of FSM state
    • Total number of state =
  • Modeling of FSM transition

N bits

Processor’s state Sk:

SS2

SS1

SSU

stall

stall

compaction of fsm model
Compaction of FSM model
  • Identifying unreachable states
    • Pass instruction to either EX1 or EX2
    • State: xx0100xx or xx0001xx ,not xx0101xx

EX1

ID

EX2

EX2

EX1

identifying illegal stage transitions
Identifying illegal stage transitions
  • Table 1
    • State: xx0001xx -> xx0101xx , not xx0001xx
  • Table 2
    • State: xx01xx -> xx00xx or xx01xx or xx11xx , not xx10xx
  • Table 3
    • State: xx11xxxx -> xx0000xx

ID

EXE

ID

EXE

normal

normal

ID

normal

normal

ID

EXE

idle

exception

idle

ID

EXE

identify redundancy
Identify redundancy
  • Inevitable state
    • Only one state in the next state list
    • Example
      • State: xx11xx -> xx00xx
      • No need state : xx01xx, xx10xx

MEM

exception

idle

test generation
Test generation
  • Coverage-driven test selection
    • StateCovered flag
      • Initial = 0
    • TransitionCovered flag
      • Initial = 0

ID

SC

idle

=0

SC

oper

=0

stall

SC

=0

=1

IF

ps

TC

=0

=1

IALU

ns

TC

=0

directed test generation 10
Directed test generation [10]
  • Multi-exception at clock cycle 7
    • overflow exception in IALU
    • divide by zero exception in DIV
    • memory exception in the MEM

Input source

Original property

Negated property

Test program

Decomposed into 3 sub-properties

experimental result of mips
Experimental result of MIPS
  • 17 function units
    • WB: 2 states
    • IALU, DIV: 4 states
    • Else: 3 states
    • Total possible states =
  • Test compaction results for MIPS processor

Remove unreachable state

Remove illegal state & redundancy

conclusion
Conclusion
  • Functional test compaction technique to reduce test program and achieve functional coverage
  • 3 methods for compaction
    • Identifying unreachable states
    • Identifying illegal stage transitions
    • Identifying inevitable state
  • My comment
    • A idea for functional verification by the state FSM
    • How to select test program to achieve 100% state and transition coverage
function coverage
Function coverage
  • State coverage
    • Visit every state
    • m units, r states, total states
  • Transition coverage
    • Visit every transition
    • N states, maximum state transitions