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The Interconnect, Control, and Instruction Decoding

The Interconnect, Control, and Instruction Decoding. CS/COE 0447 Jarrett Billingsley. Class announcements. shhhhhebang. The Interconnect. Gotta keep em separated interconnected. w e've got pieces of a CPU, but they don't operate in isolation

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The Interconnect, Control, and Instruction Decoding

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  1. The Interconnect, Control, and Instruction Decoding CS/COE 0447 Jarrett Billingsley

  2. Class announcements • shhhhhebang CS447

  3. The Interconnect CS447

  4. Gotta keep emseparated interconnected • we've got pieces of a CPU, but they don't operate in isolation • we gottahook em together. but which parts hook to which? • the instructions in the ISA tell you what has to connect to what. PC that can branch and jump Register File Data Memory ALU Instruction Memory CS447

  5. Slowly coming together • if we look at all the different instructions we want to support, we'll start to get an idea of what data goes where sub v0, t0, t1 t0 sws0, 4(t3) Register File v0 ALU - t1 s0 Register File Data Memory Data jalmove_ball t3 address ofmove_ball PC how do we make all these different things happen with one set of hardware…? Register File ra ALU + ALU? + Address 4 4 CS447

  6. PC to the left of me, ALU to the right, here I am • the interconnect lets the CPU parts combine in many ways • it's like the CPU's "circulatory system" – it moves dataaround • think about which instructions move data between which parts… Register File Data Memory PC jal stores jr loads li (immediate) add, sub, etc. Instruction Memory ALU addi, ori etc. it's starting to take shape… CS447

  7. A little technique: an interconnect matrix • you can make a table to keep track of what things connect to what. Does the data flow from here… now consider all the instructions your CPU should support, and mark the cells accordingly. …to here? sw j lw beq √ add, sub, and, or √ li? jr jal √ √ √ any component (column) with multiple things coming into it will need a MUX. (huh? next slide.) √ √ √ CS447

  8. Conjunction junction • the interconnect makes choices about which things go where only one of these is written to the register file Register File ALU results so how do we choooooose which thing to write? data from memory instruction immediates now we have a select pin. this is a control signal! saved PC for jal every MUX in the interconnect needs a control signal. 2 RegDataSrc the book calls this "MemToReg" which is a terrible name and is inconsistent with the rest of the control signal names CS447

  9. Interconnected (MIPS, not your project) • if we want to make a suuuuper simple version of MIPS, we can connect the pieces together like this: Data Memory Data (this version doesn't support jaland li, but that's fiiiine) RegWrite MemWrite rd Register File Address rs how can we use this to implement add? sub?addi? lw? sw? ALU rt RegDataSrc but now we need to, uh, control the control signals. ALUOp imm field ALUSrc CS447

  10. The Forgotten Phase:Operand Fetch CS447

  11. A little extra step • operand fetch is a phase of instruction execution you might see • it fetches the values to be operated on W M X D F O? it happens after the instruction is decoded. where do values have to be for the CPU to operate on them? in the registers…? CS447

  12. Vestigial • in MIPS (and your project), operand fetch is super simple: this is by design: load-store architectures have very simple operand fetch phases. Register File ALU why? well… imm field here it is! CS447

  13. Operand Fetch in x86 • as a CISC, x86 has some… crazy instructions. inc[eax + ecx*4 + 12] this is an effective address calculation. here's what the CPU has to do for this instruction: (the brackets mean "access memory.") multiply ecx by 4 add eax to that add 12 to that load a word from that address add 1 to that value store that value back into the address this is operand fetch. be very glad you won't have to do this for your project. CS447

  14. The Control CS447

  15. Feeling nervous • the control is what sets the write enables and selects to the appropriate values to make each instruction happen • it's like the CPU's brain and nervous system c'mon you lazy bums Control Register File it does this by reading the instructions. awwwww we don't wannaaaa 👀 sub v0, t0, t1 Data Memory Register file, read t0 and t1, and write to v0. ALU, do subtraction. Interconnect, route the data from the two registers into the ALU and from the ALU into the register file. Data memory, you get to take a break. ALU yissssss CS447

  16. Two kinds of control signals • first there are the selects • these go into the select pins of muxes, demuxes, or decoders • they can be any number of bits • then there are the write enables • these tell registers and memory when to store data • they're Booleans - 0 or 1 • they often come in pairs! • like RegWrite and RegDataSrc. • they decide what to write and when to write it. Register File RegWrite 5 rd Data Memory MemWrite RegDataSrc CS447

  17. Gotta write it down • write enables are kind of the basis of "things happening in a CPU" • almost every instruction writes something somewhere! sws0, (t0) add t0, t1, t2 writes to memory writes to t0 jalfunc1 beqs0, 10, end might write to the PC writes to the PCandra! if an instruction doesn't write anything, it's a no-op (nop). (nothing changed? then it's like the instruction never happened.) what changes when a conditional branch isn't taken? CS447

  18. The control hardware • we connected the datapath together; now for the control bits rt + 4 rd PC PCSrc target rs immediate Control instruction goes in… PCSrc Instruction Memory address goes in… …control signals come out. …instruction comes out. somehow. ALUSrc RegWrite RegDataSrc ALUOp MemWrite CS447

  19. Instruction Decoding CS447

  20. Pull 'n' peel • the first step is to split the encoded instruction up • but which instruction format is it? actually, it doesn't matter. 31-26 opcode R 25-21 rs I 20-16 32 rt 15-11 J rd 10-6 shamt "do everything at once, but use only what you need." 5-0 15-0 25-0 instruction funct immediate target CS447

  21. No, really, it's fine, don't worry about it • suppose the encoded instruction was addis0, s0, -1. op 0x08 rs put it through the splitter and… addiis an I-type instruction. 0x10 rt 0x10 opcode, rs, rt, and immediate will be used. addis0,s0,-1 rd 0x1F 32 0x2210FFFF shamt the rest are bogus and will be ignored. see? it's fiiiiiine 0x1F …out come a bunch of values. funct 0x3F imm 0xFFFF target 0x210FFFF CS447

  22. Making the control work • the control is a boolean function that takes the instruction opcode as its input and outputs the control signals. • in other words, it's a big fat truth table. I really would not recommend making your control unit like this. it's time-consuming, confusing, hard to debug, and hard to change. you will go insane. I just made up these numbers. Please don't try to use them. CS447

  23. A more approachable approach • Here's a great use for a decoder: decoding. (huh.) opcode <r-type> <uhh random crap> j these wires tell you which instruction this is. exactly one of these will be on (true) at once. jal beq bne blez now it's just a matter of coming up with the logic for each of the control signals. bgtz addi addiu for that, it's good to focus on one control signal at a time. slti sltiu CS447

  24. <the sound a seal makes> • let's say we want to come up with the MemWrite control signal • which MIPS instructions write to memory? sw this says, "if we are executing a sw, or a sh, or a sb instruction, we are writing to memory, so turn on its write enable." sh MemWrite sb what about multi-bit control signals, like the ALU operation? that might be 3 or 4 bits to select a dozen operations. there are a few approaches… CS447

  25. The brute-force approach: the MUXtipede • in this approach, you use enormous MUXes to select constants. opcode it…works, but it's hard to follow. ALUOp for opcode 0 it's hard to tell which constant is used for which instruction. ALUOp for opcode 1 ALUOp for opcode 2 ALUOp for opcode 3 it's also hard to add new instructions. ALUOp for opcode 4 ALUOp for opcode 5 ALUOp for opcode 6 ALUOp ALUOp for opcode 7 ALUOp for opcode 8 we can make this more elegant, dammit! ALUOp for opcode 9 ALUOp for opcode A ALUOp for opcode B CS447 ALUOp for opcode C

  26. Priority Encoders • apriority encoder is kind of the opposite of a decoder. • you give it several 1-bit inputs, and it tells you which one is 1. if none of the inputs is 1, then it gives you X… 0 0 0 0 1 Pri Pri Pri Pri Pri 0 1 0 0 0 0 3 1 X 2 1 0 0 0 0 0 1 0 0 0 to avoid this, put a constant 1 as the first input. CS447

  27. Multi-bit control signals • let's say we have these instructions, and these ALU operations. • for each input, ask: which instructions need this ALU operation? add addi sub subi and or 0: & 1: | 2: + 3: - ALUOp 0 is the default, so andis handled. 1 Pri which instruction(s) need OR (1)? or ALUOp add what about + (2)? addi sub what about - (3)? subi think of it like an upside-down if-else-if… CS447

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