A Novel Fixed-outline Floorplanner with Zero Deadspace for Hierarchical Design

1. A Novel Fixed-outline Floorplanner with Zero Deadspace for Hierarchical Design Ou He, Sheqin Dong, JinianBian, Satoshi Goto, Chung-Kuan Cheng Tsinghua University, Beijing, China Waseda University, Kitakyushu, Japan University of California, San Diego, La Jolla, CA ICCAD 2008

2. Outline • Introduction • Methodology • Experiment • Conclusions & Future Work

3. Outline • Introduction • Methodology • Experiment • Conclusions & Future Work

4. Introduction • Floorplanning • Two optimizations oriented: Area, Wirelength • SA is often used for solving this kind of problem • Fixed-outline floorplanning • Dominates modern hierarchical designs • Much harder than outline-free • Soft module floorplanning • Modules with a certain area but variable aspect ratios (ARs) • Achieves high area utilization (more than 99%) • Easy to implement by Linear/Quadratic Programming

5. Introduction • Prevoius work • ZDS (Zero-Dead-Space) (Cong et al, TCAD 2006) • A deterministic method with some heuristics • Very fast • Less extendable and powerful on other optimization metrics (ex: wirelength) • Convex optimization techniques (Zhan et al, ASPDAC 2006; Luo et al, ASPDAC 2008) • Able to get a global minimum • Hard to model every metric and still remain the problem convex

6. Introduction • Research motivation • Need not to minimize the area of floorplan • High area utilization means small area occupied • We can concentrate on other optimization metrics • Wirelength • Noise • Hot spot • Heat disspation • Etc.

7. Outline • Introduction • Methodology • Experiment • Conclusions & Future Work

8. Methodology • Techniques • Basic packing • Packing the modules by topological representation • Ordered Quadtree • A new topological representation • Local Refinement • Protect modules from extreme Ars • Incremental packing • Speedup the optimization

9. Methodology • Basic Packing • Place all the modules following a given topological structure • Produces zero deadspace • Handle the fixed-outline constraint in any ARs with 100% successful rate • Builds and solves a group of four quadratic equations in four variables iteratively

10. Methodology: Basic Packing • Step 1: Partitioning sub-regions • Get 8 sub-regions when placing Module i in a fixed-outline area • S1,S2,S3,S4 have two possible topological relations to Module i • There will be 16 cases for the assignment

11. Methodology: Basic Packing • Step 2: Picking up one suitable assignment of the 16 cases • One tip for the picking • The largest subset of a(i), b(i), l(i) and r(i) wins the largest number of S1, S2, S3 and S4. • where,

12. Methodology: Basic Packing • Step 3: Building the equations • A group of quadratic equations in four variables (w1, w2, h1 and h2) is built up as follows. • Finally, w1, w2, h1 and h2 will decide the coordinate and AR of Module i.

13. Methodology: Basic Packing • Step 4: Solving the equations • There are 16 different equations corresponding to 16 possible cases. • Solve the 4 children modules in sub-regions until all the modules are packed.

14. Methodology • Ordered Quadtree • Is custom-made for the basic packing to facilitate its integration to SA • Each node has four subtrees, which represent modules above, below, left to and right to the node respectively

15. Methodology: Ordered Quadtree • Perturbations on Ordered Quadtree • Subtree swap (Subtree 4 and Subtree 6) • Node migration (Node 3) • Node swap (Node 2 and Node 3) • Basic packing is called after each perturbation a b c

16. Methodology • Local Refinement • Topological Local Refinement (TLR) • Geometric Local Refinement (GLR) • Preventing modules from extreme ARs • Performed locally on a floorplan to keep an acceptable increase on the wirelength

17. Methodology: Local Refinement • Geometric Local Refinement (GLR) • Enumerates all the possible Abnormal Modules in a local sub-region of two or three modules. • Corrects those modules directly with no operations on the original ordered quadtree.

18. Methodology: Local Refinement • Topological Local Refinement (TLR) • Handles Abnormal Modules in a local sub-region of more than three modules • Changes the original quadtree and restart basic packing • More time consuming TLR Restart Basic Packing

19. Methodology • Incremental Packing • Basic packing does not need to start all over again after each perturbation. • The incremental packing can be operated from the lowest common ancestor of two perturbed branches

20. Outline • Introduction • Methodology • Experiment • Conclusions & Future Work

21. Expriment • Chip wirelength is the only optimization metric after 100% area utilization is achieved. • Compared with two Non SA-based fixed-outline floorplanners on soft modules (AR constraint [1/3, 3]) • Zhan’s work (A-FP, ASPDAC 2006) • Cong’s work (ZDS, TCAD 2006) • Compared with three SA-based outline-free floorplanners on soft modules (AR constraint [0.1, 10]) • Kim’s work (SA-CT+LP and SA-LP, TCAD 2003) • Lin’s work (SM-FP1, ICCAD 2006) • Itoga’s work (SM-FP2, IEICE 2005)

22. Expriment: non SA-based Table 1. Comparisons of Wirelength (μm) between A-FP (Zhan’s Work) and SAFFOA (our work)

23. Expriment: non SA-based Table 1(cont’d). Comparisons of wirelength (μm) between A-FP (Zhan’s Work) and SAFFOA (our work)

24. Expriment: non SA-based Table 2. Comparisons between ZDS (Cong’s work) and SAFFOA (our work)

25. Expriment: SA-based Table 3. Experimental results with SM-FP *The experimental results are updated with the permission from the author.

26. Expriment: SA-based Table 3(cont’d). Experimental results with SM-FP

27. Outline • Introduction • Methodology • Experiment • Conclusions & Future Work

28. Conclusions & Future Work • Conclusions • The FIRST SA-based Fixed-outline Floorplanner with the Optimal Area utilization named SAFFOA is implemented. • Future Work • A better local refinement will bring a great increase on the efficiency and reliability • Mixed-mode SAFFOA and 3D SAFFOA