Instrument Interface FPGA David Clarino CINEMA Space Sciences Laboratory

1. Instrument Interface FPGA • David Clarino • CINEMA • Space Sciences Laboratory • University of California, Berkeley

2. Overview • Main Uses • Abstracts control of the devices connected to the IIF as register read/writes over I2C • Buffers high volume data (STEIN, Telemetry) for convenience of DMA over SPI

3. Overview

4. Overview • MAGIC • relays commands from CPU to control MAGIC ADC • reads ADC data to register on IIF for CPU read • STEIN • pulls data from STEIN and buffers it into blocks convenient for DMA • Telemetry • Frames CCSDS Source Packets into CCSDS Transfer Frames • Reed-Solomon Encodes the Transfer Frame

5. CPU Interface Overview • I2C Interface • runs at 400 kHz • dsPIC can command IIF by writing to/reading from registers • different size registers reflect IIF’s organization of data • Uses slave address as register address • SPI Interface • DMA STEIN data from IIF, TLM data to

6. Telemetry (Overview)

7. Telemetry Framing • CCSDS Format • 1115 Byte Packet Frame Size • 255 Byte RS Codeblock size with maximum interleave of 5 • 1086 Bytes of Information • 518, 518, 50 byte CCSDS Source Packets

8. Reed-Solomon Encoder • Bit-Serial Multiplication • Berlekamp’s Bit-Serial Algorithm uses properties of finite-field arithmetic and traces to calculate the check symbol • What this translates to is a simple implementation of shift registers and a routing matrix. • The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm, Hsu, Reed, et. al • Advantages • Calculation is faster than iterative processes in the CPU • Calculation can happen “on the fly” i.e. you don’t need to know all of the bytes at one time in the codeblock in order. Saves on memory for buffering purposes • Outputs data bit-serially. No need to bit serialize data coming out of these encoders • Testing • Use C++ code to generate a 255 byte codeblock • Compare generated codeblock to codeblock generated bit-serially

9. MAGIC Control (Overview)

10. MAGIC Control (Overview) • Interface • CPU writes commands and receives MAG Vectors over I2C • IIF writes commands and receives MAG Vectors from MAGIC over SPI • Two Types of Vector Reads • X, Y, Z B-fields from either the outboard or inboard sensors • Outboard Temperature Read (Thermistor) • CPU polls at most 64 Hz • ADC is relatively “dumb” • CPU/FPGA need to initiate read. • CPU issues pseudo commands that get translated to actual MAGIC commands • Advantages: a channel read will only be a single command from the viewpoint of the CPU. Since read is initiated by CPU, relatively easy for CPU to determine what kind of data is returned by MAG

11. MAGIC Control Flow

12. STEIN Functionality • Current Status • CPU initiates all functions • IIF Buffers 508 bytes of STEIN data to be transferred to the CPU • Future • Determine handshake with CPU to offload data • Determine handshake with STEIN to pull data

13. Testing Plan • Simulation • Presynthesis: verify all VHDL works • Post-synthesis: verify synthesized VHDL works • Echo test • Use CPU to test IIF • Implement registers/blocks to bring out internal signals to CPU • Interface Test • Implement registers/blocks to verify that interface to device works • Dummy Test • Implement dummy device on FPGA to test interface • Real Test • Test actual interface to device • Same testing procedure for STEIN, MAGIC, Telemetry