Command & Data Handling System (C&DH) David McGrogan Space Sciences Laboratory

1. Command & Data Handling System (C&DH) David McGrogan Space Sciences Laboratory University of California, Berkeley

2. C&DH Agenda AGENDA Overview CPU Requirements CPU Hardware Reset Behavior Data Flow/Storage Command Upload/Storage Development Plan Issues

3. Overview SD Card Main Processor Peripherals

4. Requirements

5. CPU Microchip dsPIC33FJ256GP710 16-bit CPU 2 SPI channels (5 Mbps max) 2 UARTs (1 Mbps max) 2 I2C channels (0.4 Mbps max) 2 ECAN channels (can’t really use these) 10s of other pins (timers, ADCs, interrupts, GPIO) 30KB SRAM Useful Features Watchdog timer Brown-out reset Power-saving modes Language Support C compiler, simulator, other items are free SALVO Real-Time Operating System (unused)

6. Reset/Initialization Hardware Reset • Power-On • Watchdog Reset • Ground Command Reset Sequence • Initializes Local Data RAM to zero • Issues Initialization calls to each Module • Starts in Safe Mode (low power) • Begins Engineering Telemetry (1-sec) • Checksums available programs • Selects first program with good checksum • Waits 10 seconds • Runs selected program

7. PIC – Helium xcvr. (UART) PIC – EPS ( I2C ) PIC – SD card (SPI) PIC – FPGA (SPI) Data Paths SD CARD FPGA – Tx (bitstream) FPGA – STEIN (CDI) FPGA – MAGIC (SPI) • Peak Data Flow • Tx : 1 Mbps continuous • SDCARD : 1-2 Mbps average (including RTOS) • STEIN: 16 bits/event, 80KHz events = 1.28Mbps • MAGIC: 19 bits x 20 Hz x 3 axes = .0011 Mbps • Helium 100: 0.0096 Mbps

8. Data Movement Pipelined data flow • For high-volume data flow (STEIN and Tx) • Begin STEIN data import to DMA (512B DMA block) • Immediately begin SD card data export from DMA • Data transfer completes at maximum speed • Requires a block of DMA (512B of 2KB available on chip) Standard buffering • For smaller volumes of data (MAGIC) • Read data explicitly without DMA, store in RAM • Write to SD card when buffer sufficiently filled

9. Solid State Storage • 2 GB SD card • Holds 4.5x the amount downloadable in one pass • Blocks from 1 to 512 bytes possible • Using 512 byte blocks to minimize overhead, increase expandability (SDHC only allows 512B) • Multiple independent circular buffers for engineering, MAGIC, and STEIN data; STEIN buffer is at least half the space (>=500M 16-bit events) Eng. MAGIC STEIN

10. Command uploading and storage • 1200 Bps link through Helium • 4-byte UART FIFO would need handling at 300 Hz • 75 bytes of DMA needed for 16 Hz handling • Uploaded commands are moved to non-DMA circular buffer and handled in order • Commands execute ASAP or at a given future time (expressed in relative time)

11. Development plan Near future: • Write SD card access code • Characterize SD card read/write speed and power req.s • Establish communication protocol with FPGA

12. Issues • Warm-restart possibility – preserve local time and data across undesired resets, execute commands on time (most dsPIC registers are unaffected by a reset) • 240 mW MB draw is over ~100 mW requirement; virtually all load due to non-processor parts (e.g. line buffers), potentially different for flight board vs. dev board • Power-saving dsPIC modes available, may be irrelevant • Memory allocations (especially 2K DMA area) • Uploading multiple programs – machine code requires some effort to move in program memory (e.g. direct jumps, interrupt pointers)

14. Flight Software Veer Bawa UCB/SSL Space Sciences Laboratory University of California, Berkeley

15. Flight Software Agenda • AGENDA • Overview • Requirements • Design • Foreground Tasks • Background Timing • Modes & Enables • Actuators Development Plan Issues

16. Overview Flight Software is broken into 13 major modules: Executive (EXEC) – runs long-term tasks Background (BKG) – runs routine tasks regularly Housekeeping (HSK) – samples engineering values Load (LD) – loads/dumps memory, scans SRAM for errors Command (CMD) – decodes/distributes commands Telemetry (TM) – multiplex packets and control transmitter I/O (IO) – interface to board hardware Utilities (UTIL) – common utilities for all modules Power (PWR) – controls power supply to components Attitude Control System(ACS) – runs ACS calculations Solid State Manager(SSR) – interfaces with SD Card STEIN Control – STEIN interface MAG Control – MAG interface

17. Level 2 Requirements

18. Level 2 Requirements

19. Level 2 Requirements

20. BKG.A EXEC.A STEIN FPGA LD.A SRAM & EEPROM STEIN Elect HSK.A Analogs SPI Helium STEIN.A CMD.A STEIN Atten POWER Switches Cmds TM.A Torque Coils PWR.A COMM FPGA S-Band Tx Sun Sensors Timers ACS.A MAG FPGA MAG Elect MAG.A SDCARD SSR.A SPI SPI Simulink FSW MAJOR MODULES I II III IV Design

21. Tasks • Two kinds of tasks • Foreground tasks (called by EXEC module) • Run asynchronously in available time • No hard limit on execution time • Configurable by ground commands • ACS, SRAM scan, memory peek/poke… • Background tasks (called by BKG module) • Run at specific times • Must complete before next interrupt (~9700 instructions) • Performs tasks that must occur on time • Data flow management, MAG sampling, housekeeping ADC sampling…

22. Foreground Task Operation • Foreground tasks • Round-robin loop of standard tasks (e.g. attitude determination) • Will be frequently interrupted by background tasks, so should not rely on shared peripherals maintaining their state (may put off-chip I/O in a specialized background task) • Additional tasks can be added by commands from ground; stored in SRAM • Uploaded tasks have scheduling field – “run at time T” • Many commands can be uploaded as a burst

23. Background Timing • Timing Interrupt • 1024 Hz interrupt schedule • BKG module distributes CPU time per table • Full table repeated at 16 Hz • Table independent of mode • Each ISR checks the enable bits before running A few slots are left empty, to be used later as needed

24. Modes & Enables FSW Modes Safe – Minimal Power Configuration, Resets to Safe, all optional bits off ACS – only Flash, Torquer, and LV MAG on, Used to control attitude Science - SDCARD Allowed, STEIN, S-Band Allowed, Actuators Disabled Engineering – Everything enabled Enable Mask Table Used to Maintain Power Balance

25. Actuations • Actuators • MAG Boom • Released by .25 to .50 second pulse to unit • Actuator Enable must be commanded on • STEIN Attenuator • Moving In / Out Controlled by FSW using STEIN count rates • Damage to Attenuator if commanded to reverse direction too soon • FSW automatic lockout for 120 (commandable) seconds after actuation • UHF Antenna • - Must be automatically deployed initially, using a countdown timer • - Must ensure that reset during countdown does not affect time of • deployment adversely (i.e. too early or not at all)

26. Development Plans • Development • Pumpkin Development Board + Laptop PC • MPLAB30 “C” Compiler, Simulator, Debuggers • Subversion (SVN) for storing source code and documents • Corresponding TRAC wiki to track changes and issues (e.g. bugs) • GSE Laptop running GSEOS • FSW Developed in phases: • CPU/Mother Board Only • CPU/Mother Board + [EPS, Batt, UHF, IIB] • CPU/Mother Board + [EPS, Batt, UHF, IIB] + [HVPS,STEIN, MAG] • Verification Matrix Provides Status of Requirements • Comprehensive Performance Test on Development Board • Load into Flight System • Joins CINEMA Test Flow and Quality reporting

27. Verification • FSW Verification • CINEMA_FSW_002_Requirements.xls tracks requirement flows Development status, test overview and procedure name Note: Sample Only

28. Issues Required resources for ACS unknown; is a background task needed? SD Card overhead unknown

29. Direct Memory Access (DMA) STEIN COMM 2KB

30. SPI

31. FSW Requirements

32. FSW Requirements