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ALICE ITS-upgrade LHCC Upgrade Session, 12 March 2013 V . Manzari (INFN-Bari)

ALICE ITS-upgrade LHCC Upgrade Session, 12 March 2013 V . Manzari (INFN-Bari). Outline Update on preparation of TDRs ITS progress report Pixel chip Thinning and dicing Flip-chip mounting Mechanics. ALICE Upgrade. From L. Musa’s talk at the LHCC meeting of Dec ’12.

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ALICE ITS-upgrade LHCC Upgrade Session, 12 March 2013 V . Manzari (INFN-Bari)

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  1. ALICE ITS-upgrade LHCC Upgrade Session, 12 March 2013 V. Manzari (INFN-Bari) Outline • Update on preparation of TDRs • ITS progress report • Pixel chip • Thinning and dicing • Flip-chip mounting • Mechanics

  2. ALICE Upgrade From L. Musa’s talk at the LHCC meeting of Dec ’12 • LoI and ITS CDR presented to LHCC in Sep 2012. Next Step: • More structured organization of projects and R&D programme • Prepare 4 Technical Design Reportsgrouped as follows • (1) TDR for ITS, (2) TDR for TPC Sep 2013 • (3) TDR for electronics upgrade of TRD, TOF, PHOS and MuonSep 2013 • (4) TDR for the online systems and offline computing end 2014 • The discussion on forward trigger detectors has just started - to be decided • TDRs followed by MoU addendum (or addenda) • R&D continues throughout the process with funding agreed within projects • 2013 decision timeline for MFT, VHMPID, FOCAL • Feb/March ALICE review and approval decision • June LoI Addendum – submission to LHCC • Sep LoI Addendum – submission of revised doc to LHCC LHCC meeting - March 12th, 2013

  3. ITS progress report

  4. Pixel chip - R&D with TowerJazz technology • Vigorous R&D with TowerJazz CIS process in 2011/12 (3 MPW runs) • What has been established so far • Adequate radiation hardness • Good charge collection (detection) efficiency for pixel ~ 20μmx20μm • R&D will continue till end 2014, with the following objectives • Improve signal/noise ratio • Optimization of charge-collection diode • Increase resistivity and thickness of epi-layer • apply large reverse-bias voltagelower capacitance,smallercluster size • Study different front-end circuit and readout architectures • Reduce power consumption • Reduce integration/readout time • Circuit/layout optimization for high yield and stiching •  New Submission in Mar 2013: Engineering Run (full reticle ~ 7 cm2) LHCC meeting - March 12th, 2013

  5. Pixel chip - R&D with TowerJazz technology • Charge collection efficiencies (before/after irradiation) presented in CDR • Many new results: • example of detection efficiency measurement (Explorer chip) at PS test beam Results from December 2012 test beam. More to come from currently ongoing test beam at DESY 4 layer self-consistent telescope at PS Fake hit rate is estimated from laboratory noise measurements Very high efficiencies at low fake hit rates! LHCC meeting - March 12th, 2013

  6. R&D with TowerJazz – Next step Engineering Run (tape out 10 March) • 25 wafers with different starting material (resistivity and thickness) • Several flavors of a standard test chip layout • Large functional chips to test large matrices combined to readout circuits LHCC meeting - March 12th, 2013

  7. ER Mar 2013 – towards MISTRAL/ASTRAL (IPHC-IRFU) • Mimosa-22 THRa– single-row readout • frame integration/readout time ≤ 60 μs • 2 distinct chips (different T dimensions) • goal: validate architecture of full chain from charge • collection to signal discrimination • Mimosa-22 THRb– double-row readout • Frame integration/readout time ≤ 12 μs • Sequence derived from Mimosa-22THRa by replacing single-row with double-row rolling shutter readout • 2 discriminators per column • 2 distinct chips (different discriminators) • AROM-0 – in-pixel discrimintator • In-pixel high precision discriminator (3 different architectures) • SUZE-02 – sparsification and readout circuit • + 4 chips (MIMOSA32, MIMOSA34) – in-pixel circuit optimization MIMOSA-22 THRa MIMOSA-22 THRb SUZE-02 LHCC meeting - March 12th, 2013

  8. ER Mar 2013 - PRIORITY MATRIX / ORTOPIX (CERN) • Priority encoder – data driven architecture • In-pixel discriminator • Integration/readout time ~ 5 μs • Orthopix • 4 projections of the matrix • Discriminators at the chip periphery • Explorer – in-pixel circuit optimization ParallelRollingShutter (RAL) Priority encoder • Full array divided in sub-arrays (strixel) • 2 chips, 256 strixels, 128 pixels / strixel • Layout variants in the two chips explorer Priority encoder Orthopix explorer LHCC meeting - March 12th, 2013

  9. Thinning and Dicing • 30 wafers (8”) thinned to 50 μmand diced until March 2013 • Yield and quality study ongoing Optical metrology: IR measurement of the thickness on each die (108/wafer, MIMOSA20) IR measurement does not take into account metal and inter-metal layers of the chip MIMOSA20: 6 metal layers (~ 10 um offset) Median: 40.4 um >> 50.4 um Min: 38.1 um >> 48.1 um Max: 43.2 um >> 53.2 um LHCC meeting - March 12th, 2013

  10. Laser Soldering Preparing to build one inner layer module using silicon dummy test chips Laser Vacuum tool Tray chips Bus cable Green : top layer with daisy chain connection Red : bottom layer Hole diameter : 400 um Line width : 200 um Line spacing : 200 um LHCC meeting - March 12th, 2013

  11. ITS Layout Inner Barrel (IB): 3 layers pixels Radial position (mm): 22,28,36 Length in z (mm): 270 Nr. of modules: 12, 16, 20 Nr. of chips/module: 9 Nr. of chips/layer: 108, 144, 180 Material thickness: ~ 0.3% X0 Throughput: < 200 Mbit / seccm2 Outer Barrel (OB): 4 layers pixels Radial position (mm): 200, 220, 410, 430 Length in z (mm): 843, 1475 Nr. of modules: 48, 52, 96, 102 Nr. of chips/module: 56, 56, 98, 98 Nr. of chips/layer: 2688, 2912, 9408, 9996 Material thickness: ~ 0.8% X0 Throughput: < 6Mbit / seccm2

  12. INNER BARREL STAVE • MECHANICS &COOLING • Design optimization for material budget reduction 0.3% X/X0 Total weight: from 1.8 to 1.4 grams (reduced pipe diameter) Pipes embedded in Carbon WATER COOLING TEST RESULTS LHCC meeting - March 12th, 2013

  13. ModularityVsThermal Interface Space frame ColdPlate Submodules OUTER BARREL Carbon clamps Silicon Space frame Bus ClampedPlate Submodules LHCC meeting - March 12th, 2013

  14. OUTER BARREL PROTOTYPE COLD PLATE First prototypes LHCC meeting - March 12th, 2013

  15. PROTOTYPE Carbon clamps CLAMP Silicon Bus LHCC meeting - March 12th, 2013

  16. Chip aligner and gluing machine LHCC meeting - March 12th, 2013

  17. LHCC meeting - March 12th, 2013

  18. LHCC meeting - March 12th, 2013

  19. Summary • Preparation of the TDRs for ITS, TPC and TRD+TOF+PHOS+Muonhas started • Radiation hardness and charge collection efficiency of the Towerjazz CIS process proven to fulfil the ITS specs • Study on going of several options for the front-end and readout circuit  First Engineering Run just launched • Thinning to 50 μm and dicing of 8” wafers demonstrated to be feasible and reliable • On going development of the flip-chip mounting: from single-chip to chip arrays • Mechanics and cooling of the detector modules • Optimization of the inner barrel • First conceptual studies of the middle and outer barrels • Module assembly procedure and tooling under development

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