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RISC

RISC. Reduced Instruction Set Computer Key features Large number of general purpose registers or Use of compiler technology to optimize register use Limited and simple instruction set Emphasis on optimizing the instruction pipeline. History of RISC.

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RISC

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  1. RISC • Reduced Instruction Set Computer • Key features • Large number of general purpose registers or Use of compiler technology to optimize register use • Limited and simple instruction set • Emphasis on optimizing the instruction pipeline

  2. History of RISC • IBM 801 project – late 70s ~ early 80s • David Patterson, UC Berkeley • RISC I and RISC II • Large register sets • Forerunner of SPARC architecture • John Hennessy, Stanford U. • MIPS system • Optimizing compiler and pipelines • Hennessy and Patterson wrote a series of papers that defined the RISC movement and set the stage for the ongoing RISC vs. CISC debate

  3. Comparison of processors

  4. Driving force for CISC • Software costs far exceed hardware costs • Increasingly complex high level languages • Semantic gap: Difference between operations provided in HLLs and those provided in computer architecture • Leads to: • Large instruction sets • More addressing modes • Hardware implementations of HLL statements • e.g. CASE (switch) on VAX to close the gap.

  5. Intention of CISC • Ease compiler writing • Improve execution efficiency • As complex operations can be implemented in microcode • Support more complex HLLs • A totally different approach: Simpler architecture

  6. RISC Rationales • Making instruction set architecture close to HLL  not most effective • Best support is given by optimizing most used and most time consuming features • Large number of registers • Operand referencing optimization + locality of references  memory references reduced • Careful design of pipelines • Branch prediction etc. • Simplified (reduced) instruction set

  7. Reduced Instruction Set Architecture (1) • Why CISC? • Compiler simplification? • Disputed… • Complex machine instructions harder to exploit • Optimization more difficult • Smaller programs? • Program takes up less memory but… • Memory is now cheap • May not occupy less bits, just look shorter in symbolic form • More instructions require longer op-codes • Register references require fewer bits

  8. Reduced Instruction Set Architecture (2) • Why CISC (cont’d) • Faster programs? • More complex control unit  Larger microprogram control store  Simple instructions take longer to execute • BUT, bias towards use of simpler instructions • It is far from clear that CISC is the appropriate solution

  9. Reduced Instruction Set Architecture (3) • RISC Characteristics • One instruction per cycle • Register to register operations • Few, simple addressing modes • Few, simple instruction formats • Hardwired design (no microcode) • Fixed instruction format, fixed length, aligned on word boundary  instruction fetch optimized • More compile time/effort

  10. Reduced Instruction Set Architecture (4) • “Potential” benefits of RISC • Performance • More effective compiler optimization • Faster control unit • More effective instruction pipelining • Faster response to interrupts (Recall: when is an interrupt processed?) • VLSI implementation • Smaller area dedicated to control unit • Easier design and implementation  Shorter design and implementation time

  11. RISC vs. CISC • Many designs borrow from both philosophies • E.g. PowerPC no longer pure RISC • E.g. Pentium II and later incorporate RISC characteristics

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