1 / 6

VEPIX53: Current status

VEPIX53: Current status. Elia Conti 29/01/2014. Block diagram of the verification environment. top test lib top base test top test1,2…. top env. analysis env. hit env. readout env. trigger env. top virtual sequencer. PixelChipHarness. Clock and reset generator. PixelChip. DUT.

sasha
Download Presentation

VEPIX53: Current status

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. VEPIX53: Current status Elia Conti 29/01/2014

  2. Block diagram of the verification environment • top test lib • top base test • top test1,2… top env analysisenv hit env readoutenv trigger env top virtualsequencer PixelChipHarness Clock and resetgenerator PixelChip DUT hit_if analysis_if trig_if readout_if PixelChipInterfaces

  3. DUT Pixel Chip • PR buffer is an array of queues • Each queue stores ToA + ToT from each pixel Pixel Region (PR) PR buffer Pixel matrix ToA HITS HIT PACKETS ToT ToT conv. Digital PUC PixelChipHarness TRIGGERLOGIC ..... ..... ..... TRIGGER TIME TAG END OF COLUMN (externalToAcounter) PIXEL BUSY FLAGS PR BUFFER FULL FLAG

  4. Readout verification component (I) • readout_monitor collects PR buffer output and builds readout_trans transactions • PR buffer does not work as desired because each output is updated every time a nonzero packet is selected by trigger • Persistence of past output in readout_trans: readoutenv readout master agent readout monitor

  5. Readout verification component (II) readoutenv readout master agent readout monitor • Temporary workaround:ToAequalization of readout_trans transactionsin readout_monitor

  6. New version of PR buffer • State machine diagram reset = 0 ToA < timeTag- latency ToA > timeTag - latency dout = 0 IDLE ToA == timeTag - latency wr_en = 1 MATCH WRITE ToA == timeTag - latency fifo.push_front(packet) dout = fifo.pop_back()

More Related