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Upset Susceptibility and Design Mitigation of PowerPC405 Processors Embedded in Virtex II-Pro FPGAs

This paper discusses the upset susceptibility of PowerPC405 processors embedded in Virtex II-Pro FPGAs and explores design mitigation techniques. It compares different solutions and their impact on error robustness, design complexity, power consumption, and board area.

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Upset Susceptibility and Design Mitigation of PowerPC405 Processors Embedded in Virtex II-Pro FPGAs

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  1. Upset Susceptibility and Design Mitigation of PowerPC405 Processors Embedded in Virtex II-Pro FPGAs Gary Swift Jet Propulsion Laboratory / California Institute of Technology Gregory Allen JPL Sana Rezgui Xilinx Fayez Chayab MDA Jeff George The Aerospace Corporation Carl Carmichael Xilinx 1

  2. Background - Reconfigurable FPGA Upsets • The basic building blocks are soft to upset [Ref. 1] Thus, critical applications require both triple modular redundancy (TMR) and configuration scrubbing 2

  3. Embedded “Hard-Core” Processor(s) Upset • PowerPC 405 cores in Virtex II-Pro family FPGAs offer unprecedented computational power inside an FPGA, but include additional upsetable storage elements 3

  4. Processor Upsets – Data Cache • Processor caches are very important features for increased performance; however, upsets in the caches can lead to system errors. 4

  5. One-Chip Solution: Lockstep 1F2P [Ref. 2] 5

  6. Two-Chip Solution: Pair of Locksteps 2F4P 6

  7. Three-Chip Solution: Rad-hard Arbiter 3F+3P [Ref. 3] 7

  8. Comparison No mitigation 1-chip 2-chip 3-chip Error Robustness Design Complexity Power Consumption Board Area 8

  9. References • [1] J. George et al., “Initial Single-Event Effects Testing and Mitigation in the Xilinx Virtex II-Pro FPGA,” Paper 211, MAPLD 2005. • [2] M. Wang and G. Bolotin, “SEU Mitigation Techniques for Xilinx Virtex-II Pro FPGA,” Paper D110, MAPLD 2004, http://klabs.org/mapld04/presentations/session_d/ 1_d110_wang_s.ppt • [3] J. Lyke and B. Marty, Virtual Field Programmable Gate Array Triple Modular Redundant Cell Design, Air Force Research Laboratory: Space Vehicles Directorate, AFRL-VS-PS-TR-2004-1093, April 28, 2004. 9

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