UNIT-II Basic Circuit Concepts: Capacitance, resistance estimations-

1. UNIT-II Basic Circuit Concepts: Capacitance, resistance estimations- Sheet Resistance Rs, MOS Device Capacitances, routing Capacitance, Analytic Inverter Delays, Driving large Capacitive Loads, Fan-inand fan-out. VLSI Circuit Design Processes: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2μm CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits, Limitations of Scaling.

2. MOS circuits are formed on four basic layers: • N-diffusion • P-diffusion • Polysilicon • Metal • These layers are isolated by one another by thick or • thin silicon dioxide insulating layers. • Thin oxide mask region includes n-diffusion / p-Diffusion and transistor channel.

3. VLSI DESIGN FLOW The Y-chart ( first introduced by D. Gajski ) is shown in below figure illustrates a design flow for most logic chips, using design activities on the three different axes (domains). Y chart of three major domains, they are: • Behavioral domain • Structural domain • Geometrical layout domain

6. VLSI DESIGN FLOW CHART

7. Front-end design includes digital design using hardware description languages(HDLs), design verification through simulation and formal verification techniques, synthesis of digital designs to gates, and design for testability. Back-end design consists of CMOS library design and characterisation, physical design (floor-planning, placement and routing), design for manufacturability, packaging, test generation and fault simulation.

8. Stick diagram : • Stick diagrams may be used to convey layer information • through the use of a color code. Stick diagrams are a means of capturing topography and layer information using simple diagrams. Acts as an interface between symbolic circuit and the actual layout. A stick diagram is a cartoon of a layout.

9. Encodings for NMOS process:

10. Rules for drawing Stick Diagram Rule 1 : When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact.

11. Rule 2 : When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).

12. Rule 3: When a poly crosses diffusion it represents a transistor.

13. Rule 4 : In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.

14. Stick diagrams of nMOS :

15. nMOS Inverter :

16. nMOS NOR Gate :

17. Stick Diagram :

18. 2 input NAND Gate :

19. nMOS NAND Gate Stick Diagram :

20. nMOS F=XY+Z :

21. Encodings for CMOS process:

22. CMOS Inverter :

24. CMOS NOR Gate : VDD A B Vout

25. CMOS NOR Gate :

27. CMOS NAND Gate : VDD Vout A B

28. CMOS NAND Gate :

32. Encodings of BiCMOS :

35. nMOS Inverter Layout :

36. CMOS Inverter Layout :

44. CMOS 3 INPUT NAND GATE :

45. Layout Design Rules The physical mask layout of any circuit to be manufactured using a particular process must conform to a set of geometric constraints or rules, which are generally called layout design rules. These rules usually specify the minimum allowable line widths for physical objects on-chip such as metal and polysilicon interconnects or diffusion areas, minimum feature dimensions, and minimum allowable separations between two such features.

46. The design rules are usually described in two ways : • Micron rules, in which the layout constraints such as minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute dimensions in micrometers, or, • Lambda rules, which specify the layout constraints in terms of a single parameter (L) and, thus, allow linear, proportional scaling of all geometrical constraints.

47. Lamda based design rules :

50. Contact cuts :