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Current Status of SoC Design Lab at NCTU: Course Overview and Future Plans

This document outlines the current status and future directions of the System-on-Chip (SoC) Design Lab at NCTU, as of September 12, 2003. It details past experiences and course content from the IP Core Design courses conducted in Fall 2001 and Fall 2002, highlighting homework assignments and lab activities. The document also discusses the upcoming SoC Design Lab for Spring 2004, focusing on lab-oriented teaching and updated tools for rapid prototyping. This reflects a commitment to enhancing student learning and practical experience in electronics.

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Current Status of SoC Design Lab at NCTU: Course Overview and Future Plans

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  1. SoD Lab Current Status – NCTU EE Nelson Yen Chung Chang Department and Institute of Electronics, NCTU 2003/9/12

  2. Outline • Previous Experience • Current Plan

  3. IP Core Design 2001 • 2001 (Fall) September ~ 2002 January • Instructor: • Professor Chien-Wei Jen • TAs: • Kun-Bin Lee • Yuan-Chung Lee • Jih-Ying Lin • Nelson Yen-Chung Chang • Tzung-Shian Yang • Contents • 3 hours lecture in each week • 4 Labs • Homework • HW#1: Baseline JPEG Software Encoder: ARMulator (2 weeks) • HW#2: Baseline JPEG Software Encoder: Integrator (2 weeks) • HW#3: Virtual Prototyping of JPEG Software Encoder (2 weeks) • HW#4: Soft IP for JPEG Software Encoder (3 weeks)

  4. IP Core Design 2002 • 2002 (Fall) September ~ 2003 January • Instructor: • Professor Chien-Wei Jen • TAs: • Kun-Bin Lee • Nelson Yen-Chung Chang • Yu-Ming Chang • Hao-Yun Chin • Contents • 3 hours lecture in each week • 6 Labs • Homework • HW#1: Software Implementation of Target IP (2 weeks) • HW#2: Software Implementation Optimized for ARM Integrator Environment (2 weeks) • HW#3: Digital IP Authoring (2 weeks) • HW#4: Rapid Prototyping (3 weeks)

  5. Outline • Previous Experience • Current Plan

  6. SoC Design Lab 2004 • 2004 Spring • Instructor: • Professor Tian-Sheuang Chang • Notes: • Lab oriented • Using tools of later version • Xilinx ISE 4.1i (or 5.1i) for Rapid prototyping • Simpler work flow • Less error prone • Faster

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