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Partial Scan Design With Guaranteed Combinational ATPG. Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ 07974 va@agere.com Yong C. Kim and Kewal K. Saluja University of Wisconsin, Dept. of ECE Madison, WI 53706

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partial scan design with guaranteed combinational atpg

Partial Scan Design With Guaranteed Combinational ATPG

Vishwani D. Agrawal

Agere Systems

Processor Architectures and Compilers Research

Murray Hill, NJ 07974

va@agere.com

Yong C. Kim and Kewal K. Saluja

University of Wisconsin, Dept. of ECE

Madison, WI 53706

kimy@ece.wisc.eduand saluja@engr.wisc.edu

October 5, 2001

Agrawal, Kim and Saluja

problem statement
Problem Statement
  • Partial scan design has less DFT overhead, but is less desirable than full-scan because it requires sequential ATPG.
  • Problem: To devise a combinational ATPG method for general acyclic (cycle-free) circuits; cyclicstructures can be made acyclic by partial scan.

FF1

FF2

FF2

A cyclic circuit

Acyclic partial scan circuit

Agrawal, Kim and Saluja

overview
Overview

1. Combinational ATPG for general acyclic circuits

  • Background: Previous results and relevant ideas
  • Balanced model for combinational ATPG
  • Single-fault model for multiple-faults
  • Results

2. Special subclasses of acyclic circuits

  • Background: Definitions and ATPG properties
  • Examples
  • Results

3. Conclusion

Agrawal, Kim and Saluja

previous work atpg models for acyclic sequential circuits
Previous Work: ATPG Models for Acyclic Sequential Circuits
  • Iterative array model (Putzolu and Roth, IEEETC, 1971)
  • Duplicated fan-in logic model (Miczo, 1986)
  • Duplicated logic model (Kunzmann and Wunderlich, JETTA, 1990)
  • Balanced structure (Gupta, et al., IEEETC, 1990)
  • Pseudo-combinational model (Min and Rogers, JETTA, 1992)

Agrawal, Kim and Saluja

two relevant results
Two Relevant Results
  • Theorem (Bushnell and Agrawal, 2000):

A test for a testable non-flip-flop fault in a cycle-free (acyclic) circuit can always be found with at most dseq+1 time-frames.

  • Balanced circuit (Gupta, et al., IEEETC, 1990): An acyclic circuit is called balanced if all paths between any pair of nodes have the same sequential depth. A combinational ATPG procedure guarantees a test for any testable fault in a balanced circuit.

Agrawal, Kim and Saluja

an example
An Example

Unbalanced nodes

a

s-a-0

s-a-0

b

FF

dseq = 1

Combinational

vector

Balanced model

Single fault

0

a1

s-a-0

s-a-0

0

1

X

1/0

b1

Multiple fault

1

a0

s-a-0

1/0

1/0

1

b0

FF replaced by buffer

Test sequence: 11, 0X

Agrawal, Kim and Saluja

a combinational atpg system for general acyclic sequential circuits
A Combinational ATPG System for General Acyclic Sequential Circuits

Yes

More faults to be detected?

No

Obtain a test sequence from comb. vectors

Generate a balanced model, map faults

Generate a test vector for a target fault using combinational ATPG

Simulate the comb. model to drop detected faults

Agrawal, Kim and Saluja

a single fault model for a multiple fault
A Single-Fault Model for a Multiple-Fault

Multiple stuck-at fault: lines a and b stuck-at 1 and line c stuck-at 0.

An equivalent single stuck-at fault: output of AND gate stuck-at 1

s-a-1

s-a-1

s-a-0

s-a-1

A

a

B

b

A

a

c

B

C

b

C

c

Y. C. Kim, V. D. Agrawal, and K. K. Saluja, “Multiple Faults: Modeling, Simulation and Test,” 15th International Conf. on VLSI Design, January 2002.

Agrawal, Kim and Saluja

proof of correctness

Fault equivalence: Faulty output functions

Amf = 1

Bmf = 1

Cmf = 0

Proof of Correctness
  • Circuit equivalence: Fault-free output functions

A = a + a ·b ·!c = a

B = b + a ·b ·!c = b

C = c ·!(a ·b ·!c) = c · (!a + !b + c) =c ·(!a + !b) + c = c

  • Fault equivalence: Faulty output functions

Asf = a + 1 = 1

Bsf = b + 1 = 1

Csf = c · 0 = 0

s-a-1

s-a-1

s-a-1

s-a-1

s-a-0

A

a

B

b

A

A

a

a

c

B

B

C

b

b

C

C

c

c

Agrawal, Kim and Saluja

acyclic circuit comb atpg example

A0

1

B0

0

FF2

0

Acyclic Circuit Comb. ATPG Example

A1

5

1

B1

X: W(X) = 2

7

FF2

FF3

1

1

6

Y

B2

FF4

3

4

C2

Step 1: Levelization, assign weights to POs.

Step 2: Apply DAS to PI A and B.

Step 2: Balance with respect to PO X.

Step 2: Balance with respect to PO Y.

An example Acyclic circuit with 4 FFs

Example of multiple fault modeling.

Step 3: Replace FFs with buffers.

D1

2

FF1

A0

1

A0

B0

A0

FF2

s-a-1

s-a-1

s-a-1

s-a-1

s-a-1

s-a-1

s-a-1

0

0

1

B0

s-a-1

1

B0

FF2

0

0

1

0

FF2

A1

0

0

A

A

FF2

5

1

5

5

1

1

A1

B1

FF3

A1

FF2

X

0

X: W(X)=2

X

7

7

7

1

s-a-1

s-a-1

s-a-1

s-a-1

s-a-1

s-a-1

s-a-1

s-a-1

s-a-1

s-a-1

5

1

1

5

FF2

FF2

FF3

FF3

B1

1

FF3

B1

X

FF2

X

A

7

7

1

1

5

FF2

FF3

1

X: W(X) = 2

1

7

1

6

Y

6

6

Y: W(Y)=2

Y

FF2

FF4

FF3

1

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

1

B2

B

B

6

Y: W(Y) = 2

6

Y

FF4

FF4

FF4

3

3

3

4

4

4

B2

B2

6

Y

C2

C

C

FF4

3

3

4

4

B

C2

C2

FF4

3

4

D1

D

D

2

2

2

C

FF1

D1

D1

2

2

FF1

FF1

FF1

D

2

FF1

FF1

Agrawal, Kim and Saluja

iscas 89 benchmark circuit s5378
ISCAS ’89 Benchmark Circuit: S5378
  • Circuit statistics)
    • Number of gates: 2,781
    • Number of FFs: 179
    • Number of faults: 4,603

ATPG run on Sun Ultra Sparc 10 workstation

*TetraMax (comb. ATPG) +Gentest (seq. ATPG)

Agrawal, Kim and Saluja

acyclic partial scan iscas 89 circuits test generation results
Acyclic Partial-Scan ISCAS’89 Circuits:Test Generation Results

FC: cov. (%), FC: efficiency (%), TGT: CPU s Sun Ultra 10

*Gentest for seq. and TetraMAX for comb. ATPG

(Hitec produced equivalent FC, FE and TGT within 10% of Gentest)

Agrawal, Kim and Saluja

background subclasses of acyclic circuits
Background: Subclasses of Acyclic Circuits
  • Balanced (B) circuit:All paths between any pair of nodes (PIs, POs, gates or FFs) have the same sequential depth(Gupta, et al., IEEETC, 1990)
  • Strongly balanced (SB) circuit:A balanced circuit having the same depth from a PO to all reachable PIs (Balakrishnan and Chakradhar, VLSI Design’96)
  • Internally balanced (IB) circuit:Becomes balanced by splitting of PI fanouts (Fujiwara, et al., IEEETC, 2000)

Sequential

Acyclic

SB

Combinational

IB

B

Agrawal, Kim and Saluja

examples of acyclic subclasses
Examples of Acyclic Subclasses

A Combinational (Full-scan) requires 4 scan FFs

An example Acyclic circuit with 4 FFs

An Internally Balanced structure, requires 1 scan FF

A Strongly Balanced structure, requires 3 scan FFs

A Balanced structure, requires 2 scan FFs

FF2out

FF2out

FF2out

FF3out

FF3out

FF3out

FF3out

A

A

A

A

A

5

5

5

5

5

1

1

1

1

1

X

X

X

X

X

7

7

7

7

7

FF2in

FF2in

FF2in

FF2

FF2

FF3

FF3in

FF3in

FF3in

FF3in

FF4out

6

6

6

6

6

Y

Y

Y

Y

Y

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

D Q

B

B

B

B

B

FF4

FF4

FF4

FF4

3

3

3

3

3

4

4

4

4

4

C

C

C

C

C

FF4in

FF1out

FF1out

D

D

D

D

D

2

2

2

2

2

FF1

FF1

FF1

FF1in

FF1in

Agrawal, Kim and Saluja

number of scan ffs for acyclic subclasses
Number of Scan FFs for Acyclic Subclasses

IB: Internally balanced, B: Balanced, SB: Strongly balanced

Agrawal, Kim and Saluja

comb atpg coverages for acyclic subclasses
Comb. ATPG Coverages for Acyclic Subclasses

ATPG: TetraMAX

Gentest and Hitec produced similar coverages

Agrawal, Kim and Saluja

atpg cpu seconds for acyclic subclasses
ATPG CPU Seconds for Acyclic Subclasses

ATPG: TetraMAX (on Sun Ultra workstation)

Gentest and Hitec show similar proportions

Agrawal, Kim and Saluja

test lengths for acyclic subclasses
Test Lengths for Acyclic Subclasses

VL: Number of combinational ATPG vectors

CC: Sequential test clock cycles (x1,000) for scan sequences

Agrawal, Kim and Saluja

conclusion
Conclusion
  • Using a balanced circuit model and combinational ATPG, we can generate tests for any acyclic sequential circuit with equal or higher fault coverage and efficiency than obtained by sequential ATPG.
  • The proposed ATPG procedure provides comparable fault coverage and efficiency with significantly lower DFT (partial-scan) overhead as compared to internally balanced, balanced, strongly balanced and combinational subclasses.
  • The multiple fault model has new applications to diagnosis, logic optimization, multiply-testable faults, and bridging faults (see VLSI Design’02 paper).

Agrawal, Kim and Saluja

papers
Papers
  • Y. C. Kim, V. D. Agrawal and K. K. Saluja, “Combinational Test Generation for Acyclic Sequential Circuits using a Balanced ATPG Model,” Proc. 14th Int. Conf. VLSI Design, Jan. 2001, pp. 143-148.
  • Y. C. Kim, V. D. Agrawal and K. K. Saluja, “Combinational Test Generation for Various Classes of Acyclic Sequential Circuits,” Proc. Int. Test Conf., Oct. 2001.
  • Y. C. Kim, V. D. Agrawal and K. K. Saluja, “Multiple-Faults: Modeling, Simulation and Test,” Proc. 15th Int. Conf. VLSI Design, Jan. 2002.

Agrawal, Kim and Saluja

slide22

Thank you

Agrawal, Kim and Saluja